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Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R.S. Williams, K. Yelick, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, J. Hiller, S. Keckler, D. Klein, P. Kogge, R.S. Williams, and K. Yelick, \u201cExascale computing study: Technology challenges in achieving exascale systems,\u201d 2008."},{"key":"2","unstructured":"[2] R. Lucas, J. Ang, K. Bergman, S. Borkar, W. Carlson, L. Carrington, G. Chiu, R. Colwell, W. Dally, J. Dongarra, A. Geist, G. Grider, R. Haring, J. Hittinger, A. Hoisie, D. Klein, P. Kogge, R. Lethin, V. Sarkar, R. Schreiber, J. Shalf, T. Sterling, R. Stevens, J. Bashor, R. Brightwell, P. Coteus, E. Debenedictus, P. Franzon, S. Hemmert, J. Hiller, K.H. Kim, H. Langston, J. Laros III, S. Leyffer, R. Murphy, R. Ross, C. Webster, and S. Wild, , \u201cTop ten exascale research challenges,\u201d 2014. 10.2172\/1222713"},{"key":"3","unstructured":"[3] PDT, https:\/\/www.cs.uoregon.edu\/research\/pdt\/home.php."},{"key":"4","unstructured":"[4] TAU, https:\/\/www.cs.uoregon.edu\/research\/tau\/home.php."},{"key":"5","unstructured":"[5] Intel Corporation, \u201cIntel\u00ae 64 and IA-32 architectures software developer's manual,\u201d Sept. 2016."},{"key":"6","unstructured":"[6] GeoPM, https:\/\/github.com\/geopm."},{"key":"7","unstructured":"[7] J.H.L. III, D. DeBonis, R. Grant, S.M. Kelly, M. Levenhagen, S. Olivier, and K. Pedretti, \u201cHigh performance computing-power application programming interface specification version 1.3,\u201d May 2016."},{"key":"8","unstructured":"[8] Y. Wada, Y. He, T. Cao, and M. Kondo, \u201cThe pompp framework: From simple dsl to sophisticated power management for hpc systems,\u201d HPC Asia 2018 Poster Session, Jan. 2018."},{"key":"9","unstructured":"[9] Y. He, Y. Wada, G. Pan, and M. Kondo, \u201cSimple DSL for power-performance modeling with segmented linear models,\u201d The 48th Int. Conf. Parallel Processing (ICPP2019) Poster Session, Aug. 2019."},{"key":"10","unstructured":"[10] NVIDIA Corporation, \u201cNVML reference manual,\u201d 2015."},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] V.M. Weaver, M. Johnson, K. Kasichayanula, J. Ralph, P. Luszczek, D. Terpstra, and S. Moore, \u201cMeasuring energy and power with PAPI,\u201d Proc. 41st Int. Conf. Parallel Processing Workshops (ICPPW), pp.262-268, Sept. 2012. 10.1109\/ICPPW.2012.39","DOI":"10.1109\/ICPPW.2012.39"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] S.S. Shende and A.D. Malony, \u201cThe TAU parallel performance system,\u201d Int. J. High Performance Computing Applications, vol.20, no.2, pp.287-331, 2006. 10.1177\/1094342006064482","DOI":"10.1177\/1094342006064482"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] K.D. Lange, \u201cIdentifying shades of green: The SPECpower benchmarks,\u201d Computer, vol.42, no.3, pp.95-97, March 2009. 10.1109\/MC.2009.84","DOI":"10.1109\/MC.2009.84"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] S. Miwa and H. Nakamura, \u201cProfile-based power shifting in interconnection networks with on\/off links,\u201d Proc. Int. Conf. for High Performance Computing, Networking, Storage and Analysis (SC15), pp.37:1-37:11, Nov. 2015. 10.1145\/2807591.2807639","DOI":"10.1145\/2807591.2807639"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] N. Gholkar, F. Mueller, and B. Rountree, \u201cPower tuning HPC jobs on power-constrained systems,\u201d Proc. 2016 Int. Conf. Parallel Architectures and Compilation (PACT'16), pp.179-191, Sept. 2016. 10.1145\/2967938.2967961","DOI":"10.1145\/2967938.2967961"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] Y. Inadomi, T. Patki, K. Inoue, M. Aoyagi, B. Rountree, M. Schulz, D.K. Lowenthal, Y. Wada, K. Fukazawa, M. Ueda, M. Kondo, and I. Miyoshi, \u201cAnalyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing,\u201d Proc. Int. Conf. for High Performance Computing, Networking, Storage and Analysis (SC15), pp.78:1-78:12, Nov. 2015. 10.1145\/2807591.2807638","DOI":"10.1145\/2807591.2807638"},{"key":"17","unstructured":"[17] PomPP Library and Tools, https:\/\/github.com\/pompp\/pompp_tools."},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] H. Zhang and H. Hoffmann, \u201cMaximizing Performance Under a Power Cap: A Comparison of Hardware, Software, and Hybrid Techniques,\u201d SIGPLAN Not., vol.51, no.4, p.545-559, March 2016. 10.1145\/2954679.2872375","DOI":"10.1145\/2954679.2872375"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] E. Arima, T. Hanawa, C. Trinitis, and M. Schulz, \u201cFootprint-Aware Power Capping for Hybrid Memory Based Systems,\u201d High Performance Computing, ed. P. Sadayappan, B.L. Chamberlain, G. Juckeland, and H. Ltaief, Lect. Notes Comput. Sci., pp.347-369, Springer International Publishing, May 2020. 10.1007\/978-3-030-50743-5_18","DOI":"10.1007\/978-3-030-50743-5_18"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] T. Cao, Y. He, and M. Kondo, \u201cDemand-aware power management for power-constrained HPC systems,\u201d Proc. IEEE\/ACM 16th Int. Symp. Cluster, Cloud and Grid Computing (CCGrid 2016), pp.21-31, May 2016. 10.1109\/CCGrid.2016.25","DOI":"10.1109\/CCGrid.2016.25"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] T. Cao, W. Huang, Y. He, and M. Kondo, \u201cCooling-aware job scheduling and node allocation for overprovisioned HPC systems,\u201d Proc. 31st IEEE International Parallel and Distributed Processing Symposium (IPDPS 2017), pp.728-737, May 2017. 10.1109\/IPDPS.2017.19","DOI":"10.1109\/IPDPS.2017.19"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] R. Sakamoto, T. Cao, M. Kondo, K. Inoue, M. Ueda, T. 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Valero, \u201cRuntime-guided mitigation of manufacturing variability in power-constrained multi-socket NUMA nodes,\u201d Proc. 2016 Int. Conf. Supercomputing (ICS'16), pp.5:1-5:12, June 2016. 10.1145\/2925426.2926279","DOI":"10.1145\/2925426.2926279"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] S. Wallace, X. Yang, V. Vishwanath, W.E. Allcock, S. Coghlan, M.E. Papka, and Z. Lan, \u201cA data driven scheduling approach for power management on hpc systems,\u201d Proc. Int. Conf. for High Performance Computing, Networking, Storage and Analysis (SC16), pp.56:1-56:11, Nov. 2016. 10.1109\/SC.2016.55","DOI":"10.1109\/SC.2016.55"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] B. Wang, D. Schmidl, C. Terboven, and M.S. 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