{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,7,2]],"date-time":"2022-07-02T04:41:53Z","timestamp":1656736913068},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2022,7,1]]},"DOI":"10.1587\/transele.2021cdp0002","type":"journal-article","created":{"date-parts":[[2022,1,4]],"date-time":"2022-01-04T22:08:49Z","timestamp":1641334129000},"page":"324-333","source":"Crossref","is-referenced-by-count":0,"title":["Time-Based Current Source: A Highly Digital Robust Current Generator for Switched Capacitor Circuits"],"prefix":"10.1587","volume":"E105.C","author":[{"given":"Kentaro","family":"YOSHIOKA","sequence":"first","affiliation":[{"name":"Keio University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] B. Jann, G. Chance, A.G. Roy, A. Balakrishnan, N. Karandikar, T. Brown, X. Li, B. Davis, J.L. Ceballos, N. Tanzi, K. Hausmann, H. Yoon, Y. Huang, A. Freiman, B. Geren, P. Pawliuk, and W. Ballantyne, \u201cA 5G sub-6GHz zero-IF and mm-Wave IF transceiver with MIMO and carrier aggregation,\u201d 2019 IEEE International Solid-State Circuits Conference-(ISSCC), pp.352-354, IEEE, 2019. 10.1109\/isscc.2019.8662417","DOI":"10.1109\/ISSCC.2019.8662417"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] D.J. McLaurin, K.G. Gard, R.P. Schubert, M.J. Manglani, H. Zhu, D. Alldred, Z. Li, S.R. Bal, J. Fan, O.E. Gysel, C.M. Mayer, and T. Montalvo, \u201cA highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD\/FDD 2G\/3G\/4G\/5G macro basestations,\u201d 2018 IEEE International Solid-State Circuits Conference-(ISSCC), pp.162-164, IEEE, 2018. 10.1109\/ISSCC.2018.8310234","DOI":"10.1109\/ISSCC.2018.8310234"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] A.M.A Ali, H. Dinc, P. Bhoraskar, C. Dillon, S. Puckett, B. Gray, C. Speir, J. Lanford, J. Brunsilius, P.R. Derounian, B. Jeffries, U. Mehta, M. McShea, and R. Stop, \u201cA 14 bit 1 GS\/s RF sampling pipelined ADC with background calibration,\u201d IEEE Journal of Solid-State Circuits, vol.49, no.12, pp.2857-2867, 2014. 10.1109\/JSSC.2014.2361339","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] A.M.A. Ali, H. Dinc, P. Bhoraskar, S. Bardsley, C. Dillon, M. McShea, J.P. Periathambi, and S. Puckett, \u201cA 12-b 18-GS\/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration,\u201d IEEE Journal of Solid-State Circuits, vol.55, no.12, pp.3210-3224, 2020. 10.1109\/JSSC.2020.3023882","DOI":"10.1109\/JSSC.2020.3023882"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] J. Lagos, B. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, \u201cA single-channel, 600-MS\/s, 12-b, ringamp-based pipelined ADC in 28-nm CMOS,\u201d IEEE Journal of Solid-State Circuits, vol.54, no.2, pp.403-416, 2018. 10.1109\/JSSC.2018.2879923","DOI":"10.1109\/JSSC.2018.2879923"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] T.-C. Hung, J.-C. Wang, and T.-H. Kuo, \u201cA Calibration-Free 71.7 dB SNDR 100MS\/s 0.7 mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme,\u201d 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.256-258, IEEE, 2020. 10.1109\/ISSCC19947.2020.9063055","DOI":"10.1109\/ISSCC19947.2020.9063055"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] C. Azcona, B. Calvo, S. Celma, N. Medrano, and M.T. Sanz, \u201cPrecision CMOS current reference with process and temperature compensation,\u201d 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp.910-913, IEEE, 2014. 10.1109\/ISCAS.2014.6865284","DOI":"10.1109\/ISCAS.2014.6865284"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] D. Osipov and S. Paul, \u201cTemperature-Compensated \u03b2 Multiplier Current Reference Circuit,\u201d IEEE Transactions on Circuits and Systems II: Express Briefs, vol.64, no.10, pp.1162-1166, 2016. 10.1109\/TCSII.2016.2634779","DOI":"10.1109\/TCSII.2016.2634779"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] D. Osipov and S. Paul, Dmitry Osipov and Steffen Paul, \u201cCompact extended industrial range cmos current references,\u201d IEEE Transactions on Circuits and Systems I: Regular Papers, vol.66, no.6, pp.1998-2006, 2019. 10.1109\/TCSI.2019.2892182","DOI":"10.1109\/TCSI.2019.2892182"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] L. Wang and C. Zhan, \u201cA 0.7-V 28-nW CMOS subthreshold voltage and current reference in one simple circuit,\u201d IEEE Transactions on Circuits and Systems I: Regular Papers, vol.66, no.9, pp.3457-3466, 2019. 10.1109\/TCSI.2019.2927240","DOI":"10.1109\/TCSI.2019.2927240"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] J. Lee and S. Cho, \u201cA 1.4-\u00b5w 24.9-ppm\/\u00b0C current reference with process-insensitive temperature compensation in 0.18-\u00b5m cmos,\u201d IEEE Journal of Solid-State Circuits, vol.47, no.10, pp.2527-2533, 2012. 10.1109\/JSSC.2012.2204475","DOI":"10.1109\/JSSC.2012.2204475"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] S.K. Wadhwa and N. Chaudhry, \u201cHigh accuracy, multi-output bandgap reference circuit in 16nm finfet,\u201d 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), pp.259-262, IEEE, 2017. 10.1109\/VLSID.2017.52","DOI":"10.1109\/VLSID.2017.52"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, \u201cA CMOS bandgap reference circuit with sub-1-V operation,\u201d IEEE Journal of Solid-State Circuits, vol.34, no.5, pp.670-674, 1999. 10.1109\/4.760378","DOI":"10.1109\/4.760378"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, \u201cA 300 nW, 15 ppm\/\u00b0C, 20 ppm\/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs,\u201d IEEE Journal of solid-state circuits, vol.44, no.7, pp.2047-2054, 2009. 10.1109\/JSSC.2009.2021922","DOI":"10.1109\/JSSC.2009.2021922"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, \u201cA 1\u00b5W 600-ppm\/\u00b0C Current Reference Circuit Consisting of Subthreshold CMOS Circuits,\u201d IEEE Transactions on Circuits and Systems II: Express Briefs, vol.57, no.9, pp.681-685, 2010. 10.1109\/TCSII.2010.2056051","DOI":"10.1109\/TCSII.2010.2056051"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] W. Huang, L. Liu, and Z. Zhu, \u201cA sub-200nw all-in-one bandgap voltage and current reference without amplifiers,\u201d IEEE Transactions on Circuits and Systems II: Express Briefs, vol.68, no.1, pp.121-125, 2020. 10.1109\/TCSII.2020.3007195","DOI":"10.1109\/TCSII.2020.3007195"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] C. Wu, W.L. Goh, C.L. Kok, W. Yang, and L. Siek, \u201cA low tc, supply independent and process compensated current reference,\u201d 2015 IEEE Custom Integrated Circuits Conference (CICC), pp.1-4, IEEE, 2015. 10.1109\/CICC.2015.7338488","DOI":"10.1109\/CICC.2015.7338488"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] T. Hirose, Y. Osaki, N. Kuroki, and M. Numa, \u201cA nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities,\u201d 2010 Proceedings of ESSCIRC, pp.114-117, IEEE, 2010. 10.1109\/ESSCIRC.2010.5619819","DOI":"10.1109\/ESSCIRC.2010.5619819"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] T. Hirose, K. Ueno, N. Kuroki, and M. Numa, \u201cA CMOS bandgap and sub-bandgap voltage reference circuits for nanowatt power LSIs,\u201d 2010 IEEE Asian Solid-State Circuits Conference, pp.1-4, IEEE, 2010. 10.1109\/ASSCC.2010.5716561","DOI":"10.1109\/ASSCC.2010.5716561"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, \u201c1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs,\u201d IEEE Journal of Solid-State Circuits, vol.48, no.6, pp.1530-1538, 2013. 10.1109\/JSSC.2013.2252523","DOI":"10.1109\/JSSC.2013.2252523"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] M. Choi, I. Lee, T.-K. Jang, D. Blaauw, and D. Sylvester, \u201cA 23pW, 780ppm\/\u00b0C resistor-less current reference using subthreshold MOSFETs,\u201d ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), pp.119-122, IEEE, 2014. 10.1109\/ESSCIRC.2014.6942036","DOI":"10.1109\/ESSCIRC.2014.6942036"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] K. Yoshioka, T. Sugimoto, N. Waki, S. Kim, D. Kurose, H. Ishii, M. Furuta, A. Sai, and T. Itakura, \u201cA 0.7 V 12b 160MS\/s 12.8 fJ\/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique,\u201d 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp.478-479, IEEE, 2017. 10.1109\/ISSCC.2017.7870469","DOI":"10.1109\/ISSCC.2017.7870469"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] K. Yoshioka, T. Sugimoto, N. Waki, S. Kim, D. Kurose, H. Ishii, M. Furuta, A. Sai, H. Ishikuro, and T. Itakura, \u201cDigital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits,\u201d IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.27, no.11, pp.2575-2586, 2019. 10.1109\/TVLSI.2019.2924686","DOI":"10.1109\/TVLSI.2019.2924686"},{"key":"24","unstructured":"[24] C. Wang, \u201cAdaptive bias current generation for switched-capacitor circuits,\u201d US Patent No.7750837."},{"key":"25","unstructured":"[25] R. Kapsta, \u201cAdaptive bias current generator methods and apparatus,\u201d US Patent No.8044654."},{"key":"26","unstructured":"[26] Z. Jun, \u201cAdaptive voltage scaling using a delay line,\u201d US Patent No.8378738."},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] R. Kapusta, J. Shen, S. Decker, H. Li, E. Ibaragi, and H. Zhu, \u201cA 14b 80 Ms\/s SAR ADC with 73.6 db SNDR in 65 nm CMOS,\u201d IEEE Journal of Solid-State Circuits, vol.48, no.12, pp.3059-3066, 2013. 10.1109\/JSSC.2013.2274113","DOI":"10.1109\/JSSC.2013.2274113"},{"key":"28","unstructured":"[28] F. Thompson, \u201cUse of a DLL to optimize an ADC performance,\u201d US Patent No.8786483."},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] S. Sidiropoulos and M.A. Horowitz, \u201cA semidigital dual delay-locked loop,\u201d IEEE Journal of Solid-State Circuits, vol.32, no.11, pp.1683-1692, 1997. 10.1109\/4.641688","DOI":"10.1109\/4.641688"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] T.H. Lee, K.S. Donnelly, J.T.C. Ho, J. Zerbe, M.G. Johnson, and T. Ishikawa, \u201cA 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte\/s DRAM,\u201d IEEE Journal of Solid-State Circuits, vol.29, no.12, pp.1491-1496, 1994. 10.1109\/4.340422","DOI":"10.1109\/4.340422"},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] B. Razavi, \u201cThe delay-locked loop [A circuit for all seasons],\u201d IEEE Solid-State Circuits Magazine, vol.10, no.3, pp.9-15, 2018. 10.1109\/MSSC.2018.2844615","DOI":"10.1109\/MSSC.2018.2844615"},{"key":"32","doi-asserted-by":"publisher","unstructured":"[32] H. Kim, Y. Kim, T. Kim, H.J. Ko, and S. Cho, \u201cA 2.4-GHz 1.5-mW digital multiplying delay-locked loop using pulsewidth comparator and double injection technique,\u201d IEEE Journal of Solid-State Circuits, vol.52, no.11, pp.2934-2946, 2017. 10.1109\/JSSC.2017.2734910","DOI":"10.1109\/JSSC.2017.2734910"},{"key":"33","doi-asserted-by":"publisher","unstructured":"[33] P. Mroszczyk and P. Dudek, \u201cTunable CMOS delay gate with improved matching properties,\u201d IEEE Transactions on Circuits and Systems I: Regular Papers, vol.61, no.9, pp.2586-2595, 2014. 10.1109\/TCSI.2014.2312491","DOI":"10.1109\/TCSI.2014.2312491"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E105.C\/7\/E105.C_2021CDP0002\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,2]],"date-time":"2022-07-02T04:19:21Z","timestamp":1656735561000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E105.C\/7\/E105.C_2021CDP0002\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7,1]]},"references-count":33,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2021cdp0002","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,7,1]]},"article-number":"2021CDP0002"}}