{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,22]],"date-time":"2024-09-22T04:21:33Z","timestamp":1726978893986},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2022,10,1]]},"DOI":"10.1587\/transele.2021ctp0001","type":"journal-article","created":{"date-parts":[[2022,4,10]],"date-time":"2022-04-10T22:09:01Z","timestamp":1649628541000},"page":"544-551","source":"Crossref","is-referenced-by-count":0,"title":["4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop"],"prefix":"10.1587","volume":"E105.C","author":[{"given":"Tetsuya","family":"IIZUKA","sequence":"first","affiliation":[{"name":"Systems Design Lab., School of Engineering, The University of Tokyo"},{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meikan","family":"CHIN","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toru","family":"NAKURA","sequence":"additional","affiliation":[{"name":"Graduate School of Engineering, Fukuoka University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kunihiro","family":"ASADA","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] B. Razavi, \u201cChallenges in the design high-speed clock and data recovery circuits,\u201d IEEE Communications Magazine, vol.40, no.8, pp.94-101, 2002. 10.1109\/mcom.2002.1024421","DOI":"10.1109\/MCOM.2002.1024421"},{"key":"2","unstructured":"[2] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw Hill, Chicago, 2002."},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] M.-t. Hsieh and G.E. Sobelman, \u201cArchitectures for multi-gigabit wire-linked clock and data recovery,\u201d IEEE Circuits and Systems Magazine, vol.8, no.4, pp.45-57, 2008. 10.1109\/mcas.2008.930152","DOI":"10.1109\/MCAS.2008.930152"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] J.L Sonntag and J. Stonick, \u201cA Digital Clock and Data Recovery Architecture for Multi-Gigabit\/s Binary Links,\u201d IEEE Journal of Solid-State Circuits, vol.41, no.8, pp.1867-1875, 2006. 10.1109\/jssc.2006.875292","DOI":"10.1109\/JSSC.2006.875292"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] J. Poulton, R. Palmer, A.M. Fuller, T. Greer, J. Eyles, W.J. Dally, and M. Horowitz, \u201cA 14-mW 6.25-Gb\/s transceiver in 90-nm cmos,\u201d IEEE Journal of Solid-State Circuits, vol.42, no.12, pp.2745-2757, 2007. 10.1109\/jssc.2007.908692","DOI":"10.1109\/JSSC.2007.908692"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] P.K. Hanumolu, G.-Y. Wei, and U.-K. Moon, \u201cA Wide-Tracking Range Clock and Data Recovery Circuit,\u201d IEEE Journal of Solid-State Circuits, vol.43, no.2, pp.425-439, 2008. 10.1109\/jssc.2007.914290","DOI":"10.1109\/JSSC.2007.914290"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, and B. Del Signore, \u201cA 2.5-Gb\/s Multi-Rate 0.25-\u00b5m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog\/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition,\u201d IEEE Journal of Solid-State Circuits, vol.41, no.12, pp.2930-2944, 2006. 10.1109\/jssc.2006.884391","DOI":"10.1109\/JSSC.2006.884391"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L. DeVito, \u201cA 12.5-mb\/s to 2.7-Gb\/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,\u201d IEEE Journal of Solid-State Circuits, vol.40, no.12, pp.2713-2725, 2005. 10.1109\/jssc.2005.856577","DOI":"10.1109\/JSSC.2005.856577"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] R.-J. Yang, K.-H. Chao, S.-C. Hwu, C.-K. Liang, and S.-I. Liu, \u201cA 155.52Mbps-3.125Gbps continuous-rate clock and data recovery circuit,\u201d IEEE Journal of Solid-State Circuits, vol.41, no.6, pp.1380-1390, 2006. 10.1109\/jssc.2006.874328","DOI":"10.1109\/JSSC.2006.874328"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] G. Shu, S. Saxena, W.-S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P.K. Hanumolu, \u201cA Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop,\u201d IEEE Journal of Solid-State Circuits, vol.49, no.4, pp.1036-1047, 2014. 10.1109\/jssc.2013.2296152","DOI":"10.1109\/JSSC.2013.2296152"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] G. Shu, W.-S. Choi, S. Saxena, M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, and P.K. Hanumolu, \u201cA 4-to-10.5Gb\/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition,\u201d IEEE Journal of Solid-State Circuits, vol.51, no.2, pp.428-439, 2016. 10.1109\/jssc.2015.2497963","DOI":"10.1109\/JSSC.2015.2497963"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Y. Yano, S. Yoshida, S. Izumi, H. Kawaguchi, T. Hirose, M. Miyahara, T. Someya, K. Okada, I. Akita, Y. Kurui, H. Tomizawa, and M. Yoshimoto, \u201cAn IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment,\u201d 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.267-270, 2019. 10.1109\/a-sscc47793.2019.9056902","DOI":"10.1109\/A-SSCC47793.2019.9056902"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] D. Bol, J. De Vos, C. Hocquet, F. Botman, F. Durvaux, S. Boyd, D. Flandre, and J.D. Legat, \u201cSleepWalker: A 25-MHz 0.4-V Sub-mm<sup>2<\/sup> 7-<i>\u00b5<\/i>W\/MHz Microcontroller in 65-nm LP\/GP CMOS for Low-Carbon Wireless Sensor Nodes,\u201d IEEE Journal of Solid-State Circuits, vol.48, no.1, pp.20-32, 2013. 10.1109\/jssc.2012.2218067","DOI":"10.1109\/JSSC.2012.2218067"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] B. Leibowitz, R. Palmer, J. Poulton, Y. Frans, S. Li, J. Wilson, M. Bucher, A.M. Fuller, J. Eyles, M. Aleksic, T. Greer, and N.M. Nguyen, \u201cA 4.3GB\/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling,\u201d IEEE Journal of Solid-State Circuits, vol.45, no.4, pp.889-898, 2010. 10.1109\/jssc.2010.2040230","DOI":"10.1109\/JSSC.2010.2040230"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] K. Maruko, T. Sugioka, H. Hayashi, Z. Zhou, Y. Tsukuda, Y. Yagishita, H. Konishi, T. Ogata, H. Owa, T. Niki, K. Konda, M. Sato, H. Shiroshita, T. Ogura, T. Aoki, H. Kihara, and S. Tanaka, \u201cA 1.296-to-5.184Gb\/s Transceiver with 2.4mW\/(Gb\/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator,\u201d 2010 IEEE International Solid-State Circuits Conference-(ISSCC), pp.364-365, 2010. 10.1109\/isscc.2010.5433821","DOI":"10.1109\/ISSCC.2010.5433821"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] J. Terada, K. Nishimura, S. Kimura, H. Katsurai, N. Yoshimoto, and Y. Ohtomo, \u201cA 10.3125Gb\/s Burst-Mode CDR Circuit using a \u03b4\u03c3 DAC,\u201d 2008 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, pp.226-609, 2008. 10.1109\/isscc.2008.4523139","DOI":"10.1109\/ISSCC.2008.4523139"},{"key":"17","unstructured":"[17] C.F. Liang, S.C. Hwu, Y.H. Tu, Y.L. Yang, and H.S. Li, \u201cA reference-free, digital background calibration technique for gated-oscillator-based CDR\/PLL,\u201d 2009 Symposium on VLSI Circuits, pp.14-15, 2009."},{"key":"18","unstructured":"[18] W.-S. Choi, T. Anand, G. Shu, and P.K. Hanumolu, \u201cA fast power-on 2.2,Gb\/s burst-mode digital CDR with programmable input jitter filtering,\u201d 2013 Symposium on VLSI Circuits, pp.C280-C281, 2013."},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] S. Kaeriyama and M. Mizuno, \u201cA 10Gb\/s\/ch 50mW 120\u00d7130\u00b5m<sup>2<\/sup> clock and data recovery circuit,\u201d 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., vol.1, pp.70-478, 2003. 10.1109\/isscc.2003.1234211","DOI":"10.1109\/ISSCC.2003.1234211"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] B. Abiri, R. Shivnaraine, A. Sheikholeslami, H. Tamura, and M. Kibune, \u201cA 1-to-6Gb\/s phase-interpolator-based burst-mode CDR in 65nm CMOS,\u201d 2011 IEEE International Solid-State Circuits Conference, pp.154-156, 2011. 10.1109\/isscc.2011.5746261","DOI":"10.1109\/ISSCC.2011.5746261"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] A. Li, J. Faucher, and D. Plant, \u201cBurst-mode clock and data recovery in optical multiaccess networks using broad-band PLLs,\u201d IEEE Photonics Technology Letters, vol.18, no.1, pp.73-75, 2006. 10.1109\/lpt.2005.860396","DOI":"10.1109\/LPT.2005.860396"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] B.J. Shastri and D.V. Plant, \u201c5\/10-Gb\/s burst-mode clock and data recovery based on semiblind oversampling for pons: Theoretical and experimental,\u201d IEEE Journal of Selected Topics in Quantum Electronics, vol.16, no.5, pp.1298-1320, 2010. 10.1109\/jstqe.2010.2041326","DOI":"10.1109\/JSTQE.2010.2041326"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] C.-F. Liang and S.-I. Liu, \u201cA 20\/10\/5\/2.5Gb\/s power-scaling burst-mode cdr circuit using GVCO\/DIV2\/DFF tri-mode cells,\u201d 2008 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, pp.224-608, 2008. 10.1109\/isscc.2008.4523138","DOI":"10.1109\/ISSCC.2008.4523138"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] J.M. Lin, C.Y. Yang, and H.M. Wu, \u201cA 2.5-Gb\/s dll-based burst-mode clock and data recovery circuit with 4 \u00d7 oversampling,\u201d IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no.4, pp.791-795, 2015. 10.1109\/tvlsi.2014.2316553","DOI":"10.1109\/TVLSI.2014.2316553"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] M.-C. Su, W.-Z. Chen, P.-S. Wu, Y.-H. Chen, C.-C. Lee, and S.-J. Jou, \u201cA 10-Gb\/s, 1.24pj\/bit, burst-mode clock and data recovery with jitter suppression,\u201d IEEE Transactions on Circuits and Systems I: Regular Papers, vol.62, no.3, pp.743-751, 2015. 10.1109\/tcsi.2014.2367573","DOI":"10.1109\/TCSI.2014.2367573"},{"key":"26","doi-asserted-by":"publisher","unstructured":"[26] J. Lee and M. Liu, \u201cA 20-Gb\/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique,\u201d IEEE Journal of Solid-State Circuits, vol.43, no.3, pp.619-630, 2008. 10.1109\/jssc.2007.916598","DOI":"10.1109\/JSSC.2007.916598"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] T. Iizuka, S. Miura, Y. Ishizone, Y. Murakami, and K. Asada, \u201cA true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC,\u201d Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, pp.1-4, 2013. 10.1109\/cicc.2013.6658550","DOI":"10.1109\/CICC.2013.6658550"},{"key":"28","doi-asserted-by":"publisher","unstructured":"[28] R.B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J.L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I.Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O.E. Eliezer, E. de Obaldia, and P.T. Balsara, \u201cAll-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,\u201d IEEE Journal of Solid-State Circuits, vol.39, no.12, pp.2278-2291, Dec. 2004. 10.1109\/jssc.2004.836345","DOI":"10.1109\/JSSC.2004.836345"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] S. Henzler, Time-to-Digital Converters, Springer, Netherlands, 2010. 10.1007\/978-90-481-8628-0_6","DOI":"10.1007\/978-90-481-8628-0"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] K. Asada, T. Nakura, T. Iizuka, and M. Ikeda, \u201cTime-Domain Approach for Analog Circuits in Deep Sub-Micron LSI,\u201d IEICE Electronics Express, vol.15, no.6, pp.1-21, March 2018. 10.1587\/elex.15.20182001","DOI":"10.1587\/elex.15.20182001"},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] R. Enomoto, T. Iizuka, T. Koga, T. Nakura, and K. Asada, \u201cA 16-bit 2.0-ps Resolution Two-Step TDC in 0.18\u00b5m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration,\u201d IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.27, no.1, pp.11-19, 2019. 10.1109\/tvlsi.2018.2867505","DOI":"10.1109\/TVLSI.2018.2867505"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] T. Iizuka and K. Asada, \u201cTime-Domain Approach for Analog Circuits: Fine-Resolution TDC and Quick-Start CDR Circuits,\u201d 2018 International Conference on Advanced Technologies for Communications (ATC), pp.376-381, 2018. 10.1109\/atc.2018.8587485","DOI":"10.1109\/ATC.2018.8587485"},{"key":"33","doi-asserted-by":"crossref","unstructured":"[33] T. Iizuka, N. Tohge, S. Miura, Y. Murakami, T. Nakura, and K. Asada, \u201cA 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking,\u201d ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, pp.301-304, 2016. 10.1109\/esscirc.2016.7598302","DOI":"10.1109\/ESSCIRC.2016.7598302"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E105.C\/10\/E105.C_2021CTP0001\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,21]],"date-time":"2024-09-21T22:15:51Z","timestamp":1726956951000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E105.C\/10\/E105.C_2021CTP0001\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,1]]},"references-count":33,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2021ctp0001","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"type":"print","value":"0916-8524"},{"type":"electronic","value":"1745-1353"}],"subject":[],"published":{"date-parts":[[2022,10,1]]},"article-number":"2021CTP0001"}}