{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,23]],"date-time":"2026-02-23T23:47:10Z","timestamp":1771890430336,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2021,11,1]]},"DOI":"10.1587\/transele.2021ecp5009","type":"journal-article","created":{"date-parts":[[2021,5,13]],"date-time":"2021-05-13T22:07:36Z","timestamp":1620943656000},"page":"643-650","source":"Crossref","is-referenced-by-count":7,"title":["Low-Power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT"],"prefix":"10.1587","volume":"E104.C","author":[{"given":"Xianghong","family":"HU","sequence":"first","affiliation":[{"name":"School of Automation, Guangdong University of Technology"}]},{"given":"Hongmin","family":"HUANG","sequence":"additional","affiliation":[{"name":"School of Automation, Guangdong University of Technology"}]},{"given":"Xin","family":"ZHENG","sequence":"additional","affiliation":[{"name":"School of Automation, Guangdong University of Technology"}]},{"given":"Yuan","family":"LIU","sequence":"additional","affiliation":[{"name":"School of Automation, Guangdong University of Technology"}]},{"given":"Xiaoming","family":"XIONG","sequence":"additional","affiliation":[{"name":"Company of Chipeye Microelectronics Foshan Ltd."}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] V.S. Miller, \u201cUse of elliptic curves in cryptography,\u201d Advances in Cryptology-CRYPTO&apos;85, vol.19, no.03, pp.173-193, 1986."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] N. Koblitz, \u201cElliptic curve cryptosystems,\u201d Math. Comput., vol.48, no.177, pp.203-203, 1987. 10.1090\/s0025-5718-1987-0866109-5","DOI":"10.1090\/S0025-5718-1987-0866109-5"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] R.L. Rivest, A. Shamir, and L. Adleman, \u201cA method for obtaining digital signatures and public-key cryptosystems,\u201d Commun. ACM, vol.21, no.2, pp.120-126, 1978. DOI: 10.1145\/359340.359342 10.1145\/359340.359342","DOI":"10.1145\/359340.359342"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] X. Hu, X. Zheng, S. Zhang, S. Cai, and X. Xiong, \u201cA Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application,\u201d Electronics, vol.7, no.7, p.104, 2018. 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Lee, et al., \u201cA dual-field elliptic curve cryptographic processor with a radix-4 unified division unit,\u201d 2011 IEEE Int. Symp. Circuits Syst. (ISCAS), pp.713-716, 2011.","DOI":"10.1109\/ISCAS.2011.5937665"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] Z. Liu, D. Liu, and Zou X., \u201cAn Efficient and Flexible Hardware Implementation of the Dual-Field Elliptic Curve Cryptographic Processor,\u201d IEEE Trans. Ind. Electron., vol.64, no.3, pp.2353-2362, 2017. DOI: 10.1109\/TIE.2016.2625241 10.1109\/tie.2016.2625241","DOI":"10.1109\/TIE.2016.2625241"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] M.M. Islam, M.S. Hossain, M.K. Hasan, M. Shahjalal, and Y.M. Jang, \u201cFPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field,\u201d IEEE Access, vol.7, pp.178811-178826, 2019. DOI: 10.1109\/ACCESS. 2019.2958491. 10.1109\/access.2019.2958491","DOI":"10.1109\/ACCESS.2019.2958491"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] S. Asif, M.S. Hossain, and Y. Kong, \u201cHigh-throughput multi-key elliptic curve cryptosystem based on residue number system,\u201d IET Computers &amp; Digital Techniques, vol.11, no.5, pp.165-172, 2017. DOI: 10.1049\/iet-cdt.2016.0141 10.1049\/iet-cdt.2016.0141","DOI":"10.1049\/iet-cdt.2016.0141"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] K. Ananyi, H. Alrimeih, and D. Rakhmatov, \u201cFlexible Hardware Processor for Elliptic Curve Cryptography Over NIST Prime Fields,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst., vol.17, no.8, pp.1099-1112, Aug. 2009. DOI: 10.1109\/TVLSI.2009.2019415 10.1109\/tvlsi.2009.2019415","DOI":"10.1109\/TVLSI.2009.2019415"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] K.C.C. Loi and S.-B. Ko, \u201cScalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst., vol.23, no.11, pp.2753-2756, 2015. DOI: 10.1109\/TVLSI.2014.2375640 10.1109\/tvlsi.2014.2375640","DOI":"10.1109\/TVLSI.2014.2375640"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] Z.-U.-A. Khan and M. Benaissa, \u201cThroughput\/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA,\u201d IEEE Trans. Circuits Syst. II Exp. Briefs, vol.62, pp.1078-1082, 2015. DOI: 10.1109\/TCSII.2015.2455992 10.1109\/tcsii.2015.2455992","DOI":"10.1109\/TCSII.2015.2455992"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] D.J. 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Vanstone, \u201cGuide to Elliptic Curve Cryptography,\u201d Springer, New York, 2004. 10.1007\/0-387-23483-7_131"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] M.A. Nassar and L.A.A. El-Sayed, \u201cEfficient interleaved modular multiplication based on sign detection,\u201d AICCSA, pp.1-5, 2015. DOI: 10.1109\/AICCSA.2015.7507088. 10.1109\/aiccsa.2015.7507088","DOI":"10.1109\/AICCSA.2015.7507088"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] D. Narh Amanor, C. Paar, J. Pelzl, V. Bunimov, and M. Schimmler, \u201cEfficient hardware architectures for modular multiplication on FPGAs,\u201d FPL, pp.539-542, 2005. DOI: 10.1109\/FPL.2005.1515780. 10.1109\/fpl.2005.1515780","DOI":"10.1109\/FPL.2005.1515780"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] K. Javeed, X. Wang, and M. Scott, \u201cSerial and parallel interleaved modular multipliers on FPGA platform,\u201d FPL, pp.1-4, 2015, doi: 10.1109\/FPL.2015.7293986. 10.1109\/fpl.2015.7293986","DOI":"10.1109\/FPL.2015.7293986"},{"key":"30","unstructured":"[30] D. Narh Amanor, C. Paar, J. Pelzl, V. Bunimov, and M. Schimmler, \u201cEfficient hardware architectures for modular multiplication on FPGAs,\u201d International Conference on Field Programmable Logic and Applications, 2005, Tampere, Finland, pp.539-542, 2005. 10.1109\/fpl.2005.1515780"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E104.C\/11\/E104.C_2021ECP5009\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,6]],"date-time":"2021-11-06T03:18:27Z","timestamp":1636168707000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E104.C\/11\/E104.C_2021ECP5009\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,1]]},"references-count":30,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2021ecp5009","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,11,1]]},"article-number":"2021ECP5009"}}