{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,15]],"date-time":"2025-11-15T10:29:30Z","timestamp":1763202570196},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2022,6,1]]},"DOI":"10.1587\/transele.2021lhp0004","type":"journal-article","created":{"date-parts":[[2021,12,2]],"date-time":"2021-12-02T22:09:29Z","timestamp":1638482969000},"page":"232-243","source":"Crossref","is-referenced-by-count":3,"title":["A Metadata Prefetching Mechanism for Hybrid Memory Architectures"],"prefix":"10.1587","volume":"E105.C","author":[{"given":"Shunsuke","family":"TSUKADA","sequence":"first","affiliation":[{"name":"Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hikaru","family":"TAKAYASHIKI","sequence":"additional","affiliation":[{"name":"Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masayuki","family":"SATO","sequence":"additional","affiliation":[{"name":"Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazuhiko","family":"KOMATSU","sequence":"additional","affiliation":[{"name":"Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroaki","family":"KOBAYASHI","sequence":"additional","affiliation":[{"name":"Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] H.S.P. Wong, S. Raoux, S. Kim, J. Liang, J.P. Reifenberg, B. Rajendran, M. Asheghi, and K.E. Goodson, \u201cPhase change memory,\u201d Proc. IEEE, vol.98, no.12, pp.2201-2227, Dec. 2010. 10.1109\/JPROC.2010.2070050","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] G. Dhiman, R. Ayoub, and T. Rosing, \u201cPDRAM: A hybrid PRAM and DRAM main memory system,\u201d 2009 46th ACM\/IEEE Design Automation Conference, pp.664-669, IEEE, July 2009. 10.1145\/1629911.1630086","DOI":"10.1145\/1629911.1630086"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] X. Dong, Y. Xie, N. Muralimanohar, and N.P. Jouppi, \u201cSimple but effective heterogeneous main memory with on-chip memory controller support,\u201d SC'10: Proc. 2010 ACM\/IEEE Int. Conf. for High Performance Computing, Networking, Storage and Analysis, pp.1-11, IEEE, 2010. 10.1109\/SC.2010.50","DOI":"10.1109\/SC.2010.50"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] L.E. Ramos, E. Gorbatov, and R. Bianchini, \u201cPage placement in hybrid memory systems,\u201d Proc. Int. Conf. Supercomputing, pp.85-95, May 2011. 10.1145\/1995896.1995911","DOI":"10.1145\/1995896.1995911"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] J. Sim, A.R. Alameldeen, Z. Chishti, C. Wilkerson, and H. Kim, \u201cTransparent hardware management of stacked dram as part of memory,\u201d 2014 47th Annual IEEE\/ACM Int. Symp. Microarchitecture, pp.13-24, IEEE, 2014. 10.1109\/MICRO.2014.56","DOI":"10.1109\/MICRO.2014.56"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] A. Sodani, R. Gramunt, J. Corbal, H.S. Kim, K. Vinod, S. Chinthamani, S. Hutsell, R. Agarwal, and Y.C. Liu, \u201cKnights landing: Second-generation intel xeon phi product,\u201d IEEE Micro, vol.36, no.2, pp.34-46, March-April 2016. 10.1109\/MM.2016.25","DOI":"10.1109\/MM.2016.25"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] V. Mironov, I. Chernykh, I. Kulikov, A. Moskovsky, E. Epifanovsky, and A. Kudryavtsev, \u201cPerformance evaluation of the intel optane dc memory with scientific benchmarks,\u201d 2019 IEEE\/ACM Workshop on Memory Centric High Performance Computing (MCHPC), pp.1-6, 2019. 10.1109\/MCHPC49590.2019.00008","DOI":"10.1109\/MCHPC49590.2019.00008"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] G.H. Loh, Y. Xie, and B. Black, \u201cProcessor design in 3D die-stacking technologies,\u201d IEEE Micro, vol.27, no.3, pp.31-48, May-June 2007. 10.1109\/MM.2007.59","DOI":"10.1109\/MM.2007.59"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] M.K. Qureshi and G.H. Loh, \u201cFundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design,\u201d 2012 45th Annual IEEE\/ACM Int. Symp. Microarchitecture, pp.235-246, IEEE, 2012. 10.1109\/MICRO.2012.30","DOI":"10.1109\/MICRO.2012.30"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] D. Jevdjic, S. Volos, and B. Falsafi, \u201cDie-stacked dram caches for servers: Hit ratio, latency, or bandwidth? have it all with footprint cache,\u201d ACM SIGARCH Computer Architecture News, vol.41, no.3, pp.404-415, June 2013. 10.1145\/2508148.2485957","DOI":"10.1145\/2508148.2485957"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] D. Jevdjic, G.H. Loh, C. Kaynak, and B. Falsafi, \u201cUnison cache: A scalable and effective die-stacked DRAM cache,\u201d 2014 47th Annual IEEE\/ACM Int. Symp. Microarchitecture, pp.25-37, IEEE, 2014. 10.1109\/MICRO.2014.51","DOI":"10.1109\/MICRO.2014.51"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] Y. Lee, J. Kim, H. Jang, H. Yang, J. Kim, J. Jeong, and J.W. Lee, \u201cA fully associative, tagless dram cache,\u201d ACM SIGARCH Computer Architecture News, vol.43, no.3S, pp.211-222, June 2015. 10.1145\/2872887.2750383","DOI":"10.1145\/2872887.2750383"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] X. Yu, C.J. Hughes, N. Satish, O. Mutlu, and S. Devadas, \u201cBanshee: Bandwidth-efficient dram caching via software\/hardware cooperation,\u201d 2017 50th Annual IEEE\/ACM Int. Symp. Microarchitecture (MICRO), pp.1-14, IEEE, Oct. 2017. 10.1145\/3123939.3124555","DOI":"10.1145\/3123939.3124555"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] N. Gulur, M. Mehendale, R. Manikantan, and R. Govindarajan, \u201cBi-modal dram cache: Improving hit rate, hit latency and bandwidth,\u201d 2014 47th Annual IEEE\/ACM Int. Symp. Microarchitecture, pp.38-50, IEEE, 2014. 10.1109\/MICRO.2014.36","DOI":"10.1109\/MICRO.2014.36"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] S. Franey and M. Lipasti, \u201cTag tables,\u201d 2015 IEEE 21st international symposium on high performance computer architecture (hpca), pp.514-525, IEEE, 2015. 10.1109\/HPCA.2015.7056059","DOI":"10.1109\/HPCA.2015.7056059"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] H. Liu, Y. Chen, X. Liao, H. Jin, B. He, L. Zheng, and R. Guo, \u201cHardware\/software cooperative caching for hybrid dram\/nvm memory architectures,\u201d Proc. Int. Conf. Supercomputing, pp.1-10, June 2017. 10.1145\/3079079.3079089","DOI":"10.1145\/3079079.3079089"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] J. Meza, J. Chang, H. Yoon, O. Mutlu, and P. Ranganathan, \u201cEnabling efficient and scalable hybrid memories using fine-granularity dram cache management,\u201d IEEE Comput. Archit. Lett., vol.11, no.2, pp.61-64, July-Dec. 2012. 10.1109\/L-CA.2012.2","DOI":"10.1109\/L-CA.2012.2"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] H. Jang, Y. Lee, J. Kim, Y. Kim, J. Kim, J. Jeong, and J.W. Lee, \u201cEfficient footprint caching for tagless dram caches,\u201d 2016 IEEE Int. Symp. High Performance Computer Architecture (HPCA), pp.237-248, IEEE, 2016. 10.1109\/HPCA.2016.7446068","DOI":"10.1109\/HPCA.2016.7446068"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] C. Chou, A. Jaleel, and M.K. Qureshi, \u201cBear: Techniques for mitigating bandwidth bloat in gigascale dram caches,\u201d ACM SIGARCH Computer Architecture News, vol.43, no.3S, pp.198-210, June 2015. 10.1145\/2872887.2750387","DOI":"10.1145\/2872887.2750387"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] M.R. Meswani, S. Blagodurov, D. Roberts, J. Slice, M. Ignatowski, and G.H. Loh, \u201cHeterogeneous memory architectures: A HW\/SW approach for mixing die-stacked and off-package memories,\u201d 2015 IEEE 21st Int. Symp. High Performance Computer Architecture (HPCA), pp.126-136, IEEE, 2015. 10.1109\/HPCA.2015.7056027","DOI":"10.1109\/HPCA.2015.7056027"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] A. Prodromou, M. Meswani, N. Jayasena, G. Loh, and D.M. Tullsen, \u201cMempod: A clustered architecture for efficient and scalable migration in flat address space multi-level memories,\u201d 2017 IEEE Int. Symp. High Performance Computer Architecture (HPCA), pp.433-444, IEEE, 2017. 10.1109\/HPCA.2017.39","DOI":"10.1109\/HPCA.2017.39"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] J.B. Kotra, H. Zhang, A.R. Alameldeen, C. Wilkerson, and M.T. Kandemir, \u201cChameleon: A dynamically reconfigurable heterogeneous memory system,\u201d 2018 51st Annual IEEE\/ACM Int. Symp. Microarchitecture (MICRO), pp.533-545, IEEE, 2018. 10.1109\/MICRO.2018.00050","DOI":"10.1109\/MICRO.2018.00050"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] C.C. Chou, A. Jaleel, and M.K. Qureshi, \u201cCameo: A two-level memory organization with capacity of main memory and flexibility of hardware-managed cache,\u201d Proc. Micro, pp.1-12, 2014. 10.1109\/MICRO.2014.63","DOI":"10.1109\/MICRO.2014.63"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] J.H. Ryoo, M.R. Meswani, A. Prodromou, and L.K. John, \u201cSilc-fm: Subblocked interleaved cache-like flat memory organization,\u201d 2017 IEEE Int. Symp. High Performance Computer Architecture (HPCA), pp.349-360, IEEE, 2017. 10.1109\/HPCA.2017.20","DOI":"10.1109\/HPCA.2017.20"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] S. Lee, H. Bahn, and S.H. Noh, \u201cClock-dwf: A write-history-aware page replacement algorithm for hybrid pcm and dram memory architectures,\u201d IEEE Trans. Comput., vol.63, no.9, pp.2187-2200, Sept. 2013. 10.1109\/TC.2013.98","DOI":"10.1109\/TC.2013.98"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] R. Salkhordeh and H. Asadi, \u201cAn operating system level data migration scheme in hybrid dram-nvm memory architecture,\u201d 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.936-941, IEEE, 2016. 10.3850\/9783981537079_0605","DOI":"10.3850\/9783981537079_0605"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] A. Kokolis, D. Skarlatos, and J. Torrellas, \u201cPageseer: Using page walks to trigger page swaps in hybrid memory systems,\u201d 2019 IEEE Int. Symp. High Performance Computer Architecture (HPCA), pp.596-608, IEEE, 2019. 10.1109\/HPCA.2019.00012","DOI":"10.1109\/HPCA.2019.00012"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] E. Vasilakis, V. Papaefstathiou, P. Trancoso, and I. Sourdis, \u201cHybrid2: Combining caching and migration in hybrid memory systems,\u201d 2020 IEEE Int. Symp. High Performance Computer Architecture (HPCA), pp.649-662, IEEE, 2020. 10.1109\/HPCA47549.2020.00059","DOI":"10.1109\/HPCA47549.2020.00059"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] N. Binkert, B. Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, D.A. Wood, \u201cThe gem5 simulator,\u201d ACM SIGARCH computer architecture news, vol.39, no.2, pp.1-7, May 2011. 10.1145\/2024716.2024718","DOI":"10.1145\/2024716.2024718"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] S. Rashidi, M. Jalili, and H. Sarbazi-Azad, \u201cA survey on pcm lifetime enhancement schemes,\u201d ACM Comput. Surv. (CSUR), vol.52, no.4, pp.1-38, July 2019. 10.1145\/3332257","DOI":"10.1145\/3332257"},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] J.L. Henning, \u201cSpec cpu2006 benchmark descriptions,\u201d ACM SIGARCH Computer Architecture News, vol.34, no.4, pp.1-17, Sept. 2006. 10.1145\/1186736.1186737","DOI":"10.1145\/1186736.1186737"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] R. Panda, S. Song, J. Dean, and L.K. John, \u201cWait of a decade: Did spec cpu 2017 broaden the performance horizon?,\u201d 2018 IEEE Int. Symp. High Performance Computer Architecture (HPCA), pp.271-282, IEEE, 2018. 10.1109\/HPCA.2018.00032","DOI":"10.1109\/HPCA.2018.00032"},{"key":"33","unstructured":"[33] Advanced Micro Devices, AMD64 Architecture Programmer's Manual Volume 2: System Programming, March 2021."}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E105.C\/6\/E105.C_2021LHP0004\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,4]],"date-time":"2022-06-04T04:14:16Z","timestamp":1654316056000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E105.C\/6\/E105.C_2021LHP0004\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,1]]},"references-count":33,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2021lhp0004","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,6,1]]},"article-number":"2021LHP0004"}}