{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,27]],"date-time":"2025-07-27T07:55:42Z","timestamp":1753602942871},"reference-count":38,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2022,6,1]]},"DOI":"10.1587\/transele.2021sep0002","type":"journal-article","created":{"date-parts":[[2021,12,2]],"date-time":"2021-12-02T22:09:29Z","timestamp":1638482969000},"page":"264-269","source":"Crossref","is-referenced-by-count":1,"title":["A High-Speed Interface Based on a Josephson Latching Driver for Adiabatic Quantum-Flux-Parametron Logic"],"prefix":"10.1587","volume":"E105.C","author":[{"given":"Fumihiro","family":"CHINA","sequence":"first","affiliation":[{"name":"National Institute of Information and Communications Technology (NICT)"}]},{"given":"Naoki","family":"TAKEUCHI","sequence":"additional","affiliation":[{"name":"National Institute of Advanced Industrial Science and Technology (AIST)"}]},{"given":"Hideo","family":"SUZUKI","sequence":"additional","affiliation":[{"name":"Yokohama National University"}]},{"given":"Yuki","family":"YAMANASHI","sequence":"additional","affiliation":[{"name":"Yokohama National University"}]},{"given":"Hirotaka","family":"TERAI","sequence":"additional","affiliation":[{"name":"National Institute of Information and Communications Technology (NICT)"}]},{"given":"Nobuyuki","family":"YOSHIKAWA","sequence":"additional","affiliation":[{"name":"Yokohama National University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] K.K. Likharev and V.K. Semenov, \u201cRSFQ logic\/memory family: A new Josephson-junction technology for digital systems,\u201d IEEE Trans. Appl. Supercond., vol.1, no.1, pp.3-28, March 1991. DOI: 10.1109\/77.80745 10.1109\/77.80745","DOI":"10.1109\/77.80745"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] W. Chen, A.V. Rylyakov, V. Patel, J.E. Lukens, and K.K. Likharev, \u201cRapid single flux quantum T-flip flop operating up to 770GHz,\u201d IEEE Trans. Appl. Supercond., vol.9, no.2, pp.3212-3215, June 1999. DOI: 10.1109\/77.783712 10.1109\/77.783712","DOI":"10.1109\/77.783712"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] M. Tanaka, H. Akaike, A. Fujimaki, Y. Yamanashi, N. Yoshikawa, S. Nagasawa, K. Takagi, and N. Takagi, \u201c100-GHz single-flux-quantum bit-serial adder based on 10-kA\/cm<sup>2<\/sup> niobium process,\u201d IEEE Trans. Appl. Supercond., vol.21, no.3, pp.792-796, June 2011. DOI: 10.1109\/TASC.2010.2101034 10.1109\/TASC.2010.2101034","DOI":"10.1109\/TASC.2010.2101034"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] T.V. Filippov, A. Sahu, A.F. Kirichenko, I.V. Vernik, M. Dorojevets, C.L. Ayala, and O.A. Mukhanov, \u201c20GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit,\u201d Phys. Procedia, vol.36, pp.59-65, 2012. DOI: 10.1016\/j.phpro.2012.06.130 10.1016\/j.phpro.2012.06.130","DOI":"10.1016\/j.phpro.2012.06.130"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] R. Kashima, I. Nagaoka, M. Tanaka, T. Yamashita, and A. Fujimaki, \u201c64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure,\u201d IEEE Trans. Appl. Supercond., vol.31, no.5, pp.1-6, Article no.1301006, Aug. 2021. DOI: 10.1109\/TASC.2021.3061353 10.1109\/TASC.2021.3061353","DOI":"10.1109\/TASC.2021.3061353"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] Y. Sakashita, Y. Yamanashi, and N. Yoshikawa, \u201cHigh-speed operation of an SFQ Butterfly processing circuit for FFT processors using the 10kA\/cm<sup>2<\/sup> Nb process,\u201d IEEE Trans. Appl. Supercond., vol.25, no.3, pp.1-5, Article no.1301205, June 2015. DOI: 10.1109\/TASC.2014.2384833 10.1109\/TASC.2014.2384833","DOI":"10.1109\/TASC.2014.2384833"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] S.K. Tolpygo, D. Yohannes, R.T. Hunt, J.A. Vivalda, D. Donnelly, D. Amparo, and A.F. Kirichenko, \u201c20 kA\/cm<sup>2<\/sup> process development for superconducting integrated circuits with 80GHz clock frequency,\u201d IEEE Trans. Appl. Supercond., vol.17, no.2, pp.946-951, June 2007. DOI: 10.1109\/TASC.2007.898571 10.1109\/TASC.2007.898571","DOI":"10.1109\/TASC.2007.898571"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] M. Tanaka, A. Kitayama, T. Koketsu, M. Ito, and A. Fujimaki, \u201cLow-energy consumption RSFQ circuits driven by low voltages,\u201d IEEE Trans. Appl. Supercond., vol.23, no.3, Article no.1701104, June 2013. DOI: 10.1109\/TASC.2013.2240555 10.1109\/TASC.2013.2240555","DOI":"10.1109\/TASC.2013.2240555"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] D.E. Kirichenko, S. Sarwana, and A.F. Kirichenko, \u201cZero static power dissipation biasing of RSFQ circuits,\u201d IEEE Trans. Appl. Supercond., vol.21, no.3, pp.776-779, June 2011. DOI: 10.1109\/ TASC.2010.2098432 10.1109\/TASC.2010.2098432","DOI":"10.1109\/TASC.2010.2098432"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] O.A. Mukhanov, \u201cEnergy-efficient single flux quantum technology,\u201d IEEE Trans. Appl. Supercond., vol.21, no.3, pp.760-769, June 2011. DOI: 10.1109\/TASC.2010.2096792 10.1109\/TASC.2010.2096792","DOI":"10.1109\/TASC.2010.2096792"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] Q.P. Herr, A.Y. Herr, O.T. Oberg, and A.G. Ioannidis, \u201cUltra-low-power superconductor logic,\u201d J. Appl. Phys., vol.109, no.10, 103903, May 2011. DOI: 10.1063\/1.3585849 10.1063\/1.3585849","DOI":"10.1063\/1.3585849"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] T. Kamiya, M. Tanaka, K. Sano, and A. Fujimaki, \u201cEnergy\/ space-efficient rapid single-flux-quantum circuits by using \u03c0-shifted Josephson junctions,\u201d IEICE Trans. Electron., vol.E101-C, no.5, pp.385-390, May 2018. DOI: 10.1587\/transele.E101.C.385 10.1587\/transele.E101.C.385","DOI":"10.1587\/transele.E101.C.385"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] M. Hosoya, W. Hioe, J. Casas, R. Kamikawai, Y. Harada, Y. Wada, H. Nakane, R. Suda, and E. Goto, \u201cQuantum flux parametron: A single quantum flux device for Josephson supercomputer,\u201d IEEE Trans. Appl. Supercond., vol.1, no.2, pp.77-89, June 1991. DOI: 10.1109\/ 77.84613 10.1109\/77.84613","DOI":"10.1109\/77.84613"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] N. Takeuchi, D. Ozawa, Y. Yamanashi, and N. Yoshikawa, \u201cAn adiabatic quantum flux parametron as an ultra-low-power logic device,\u201d Supercond. Sci. Technol., vol.26, no.3, 035010, March 2013. DOI: 10.1088\/0953-2048\/26\/3\/035010 10.1088\/0953-2048\/26\/3\/035010","DOI":"10.1088\/0953-2048\/26\/3\/035010"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, \u201cMeasurement of 10 zJ energy dissipation of adiabatic quantum-flux-parametron logic using a superconducting resonator,\u201d Appl. Phys. Lett., vol.102, no.5, 052602, Feb. 2013. DOI: 10.1063\/1.4790276 10.1063\/1.4790276","DOI":"10.1063\/1.4790276"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] Y. Yamanashi, T. Matsushima, N. Takeuchi, N. Yoshikawa, and T. Ortlepp, \u201cEvaluation of current sensitivity of quantum flux parametron,\u201d Supercond. Sci. Technol., vol.30, no.8, 084004, Aug. 2017. DOI: 10.1088\/1361-6668\/aa73be 10.1088\/1361-6668\/aa73be","DOI":"10.1088\/1361-6668\/aa73be"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] C.L. Ayala, T. Tanaka, R. Saito, M. Nozoe, N. Takeuchi, and N. Yoshikawa, \u201cMANA: A Monolithic Adiabatic iNtegration Architecture microprocessor using 1.4-zJ\/op unshunted superconductor Josephson junction devices,\u201d IEEE J. Solid-State Circuits, vol.56, no.4, pp.1152-1165, April 2021. DOI: 10.1109\/JSSC.2020.3041338 10.1109\/JSSC.2020.3041338","DOI":"10.1109\/JSSC.2020.3041338"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] O. Chen, R. Cai, Y. Wang, F. Ke, T. Yamae, R. Saito, N. Takeuchi, and N. Yoshikawa, \u201cAdiabatic quantum-flux-parametron: Towards building extremely energy-efficient circuits and systems,\u201d Sci. Rep., vol.9, no.1, 10514, Dec. 2019. DOI: 10.1038\/s41598-019-46595-w 10.1038\/s41598-019-46595-w","DOI":"10.1038\/s41598-019-46595-w"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] N. Takeuchi, T. Yamashita, S. Miyajima, S. Miki, N. Yoshikawa, and H. Terai, \u201cAdiabatic quantum-flux-parametron interface for the readout of superconducting nanowire single-photon detectors,\u201d Opt. Express, vol.25, no.26, pp.32650-32658, Dec. 2017. DOI: 10.1364\/OE.25.032650 10.1364\/OE.25.032650","DOI":"10.1364\/OE.25.032650"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] N. Takeuchi, F. China, S. Miki, S. Miyajima, M. Yabuno, N. Yoshikawa, and H. Terai, \u201cScalable readout interface for superconducting nanowire single-photon detectors using AQFP and RSFQ logic families,\u201d Opt. Express, vol.28, no.11, pp.15824-15834, May 2020. DOI: 10.1364\/OE.392507 10.1364\/OE.392507","DOI":"10.1364\/OE.392507"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] R.N. Tadros, A. Fayyazi, M. Pedram, and P.A. Beerel, \u201cSystemVerilog modeling of SFQ and AQFP circuits,\u201d IEEE Trans. Appl. Supercond., vol.30, no.2, pp.1-13, Article no.1300513, March 2020. DOI: 10.1109\/TASC.2019.2957196 10.1109\/TASC.2019.2957196","DOI":"10.1109\/TASC.2019.2957196"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] N. Takeuchi, H. Suzuki, and N. Yoshikawa, \u201cMeasurement of low bit-error-rates of adiabatic quantum-flux-parametron logic using a superconductor voltage driver,\u201d Appl. Phys. Lett., vol.110, no.20, 202601, May 2017. DOI: 10.1063\/1.4983351 10.1063\/1.4983351","DOI":"10.1063\/1.4983351"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] N. Takeuchi, M. Nozoe, Y. He, and N. Yoshikawa, \u201cLow-latency adiabatic superconductor logic using delay-line clocking,\u201d Appl. Phys. Lett., vol.115, no.7, 072601, Aug. 2019. DOI: 10.1063\/1.5111599 10.1063\/1.5111599","DOI":"10.1063\/1.5111599"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] T. Yamae, N. Takeuchi, and N. Yoshikawa, \u201cAdiabatic quantum-flux-parametron with delay-line clocking: Logic gate demonstration and phase skipping operation,\u201d arXiv:2107.12020, July 2021. 10.48550\/arXiv.2107.12020","DOI":"10.1088\/1361-6668\/ac2e9f"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] O.A. Mukhanov, S.V. Rylov, D.V. Gaidarenko, N.B. Dubash, and V.V. Borzenets, \u201cJosephson output interfaces for RSFQ circuits,\u201d IEEE Trans. Appl. Supercond., vol.7, no.2, pp.2826-2831, June 1997. DOI: 10.1109\/77.621825 10.1109\/77.621825","DOI":"10.1109\/77.621825"},{"key":"26","doi-asserted-by":"publisher","unstructured":"[26] N.B. Dubash, V.V. Borzenets, Y.M. Zhang, V. Kaplunenko, J.W. Spargo, A.D. Smith, and T. Van Duzer, \u201cSystem demonstration of a multigigabit network switch,\u201d IEEE Trans. Microw. Theory Tech., vol.48, no.7, pp.1209-1215, July 2000. DOI: 10.1109\/22.853461 10.1109\/22.853461","DOI":"10.1109\/22.853461"},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] I.I. Soloviev, M.R. Rafique, H. Engseth, and A. Kidiyarova-Shevchenko, \u201cHigh voltage driver for RSFQ digital signal processor,\u201d IEEE Trans. Appl. Supercond., vol.17, no.2, pp.470-473, June 2007. DOI: 10.1109\/TASC.2007.898070 10.1109\/TASC.2007.898070","DOI":"10.1109\/TASC.2007.898070"},{"key":"28","doi-asserted-by":"publisher","unstructured":"[28] Y. Hashimoto, H. Suzuki, S. Nagasawa, M. Maruyama, K. Fujiwara, and M. Hidaka, \u201cMeasurement of superconductive voltage drivers up to 25Gb\/s\/ch,\u201d IEEE Trans. Appl. Supercond., vol.19, no.3, pp.1022-1025, June 2009. DOI: 10.1109\/TASC.2009.2017867 10.1109\/TASC.2009.2017867","DOI":"10.1109\/TASC.2009.2017867"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] H. Terai, S. Miki, and Z. Wang, \u201cReadout electronics using single-flux-quantum circuit technology for superconducting single-photon detector array,\u201d IEEE Trans. Appl. Supercond., vol.19, no.3, pp.350-353, June 2009. DOI: 10.1109\/TASC.2009.2019029 10.1109\/TASC.2009.2019029","DOI":"10.1109\/TASC.2009.2019029"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] H. Suzuki, T. Imamura, and S. Hasuo, \u201cApplications of synchronized switching in series-parallel-connected Josephson junctions,\u201d IEEE Trans. Electron Devices, vol.37, no.11, pp.2399-2405, Nov. 1990. DOI: 10.1109\/16.62299 10.1109\/16.62299","DOI":"10.1109\/16.62299"},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] H. Nakagawa, E. Sogawa, S. Kosaka, S. Takada, and H. Hayakawa, \u201cOperating characteristics of Josephson four-junction logic (4JL) gate,\u201d Jpn. J. Appl. Phys., vol.21, no.4A, pp.L198-L200, 1982. DOI: 10.1143\/JJAP.21.L198 10.1143\/JJAP.21.L198","DOI":"10.1143\/JJAP.21.L198"},{"key":"32","doi-asserted-by":"publisher","unstructured":"[32] S. Takada, S. Kosaka, and H. Hayakawa, \u201cCurrent injection logic gate with four Josephson junctions,\u201d Jpn. J. Appl. Phys., vol.19, no.S1, 607, Jan. 1980. DOI: 10.7567\/JJAPS.19S1.607 10.7567\/JJAPS.19S1.607","DOI":"10.7567\/JJAPS.19S1.607"},{"key":"33","doi-asserted-by":"publisher","unstructured":"[33] T. Ortlepp, L. Zheng, S.R. Whiteley, and T. Van Duzer, \u201cDesign guidelines for Suzuki stacks as reliable high-speed Josephson voltage drivers,\u201d Supercond. Sci. Technol., vol.26, no.3, 035007, March 2013. DOI: 10.1088\/0953-2048\/26\/3\/035007 10.1088\/0953-2048\/26\/3\/035007","DOI":"10.1088\/0953-2048\/26\/3\/035007"},{"key":"34","doi-asserted-by":"publisher","unstructured":"[34] F. China, T. Narama, N. Takeuchi, T. Ortlepp, Y. Yamanashi, and N. Yoshikawa, \u201cDesign and demonstration of interface circuits between rapid single-flux-quantum and adiabatic quantum-flux-parametron circuits,\u201d IEEE Trans. Appl. Supercond., vol.26, no.5, pp.1-5, Article no.1301305, Aug. 2016. DOI: 10.1109\/TASC.2016.2577603 10.1109\/TASC.2016.2577603","DOI":"10.1109\/TASC.2016.2577603"},{"key":"35","doi-asserted-by":"publisher","unstructured":"[35] N. Takeuchi, S. Nagasawa, F. China, T. Ando, M. Hidaka, Y. Yamanashi, and N. Yoshikawa, \u201cAdiabatic quantum-flux-parametron cell library designed using a 10 kA cm<sup>-2<\/sup> niobium fabrication process,\u201d Supercond. Sci. Technol., vol.30, no.3, 035002, March 2017. DOI: 10.1088\/1361-6668\/aa52f3 10.1088\/1361-6668\/aa52f3","DOI":"10.1088\/1361-6668\/aa52f3"},{"key":"36","doi-asserted-by":"publisher","unstructured":"[36] H. Suzuki, N. Takeuchi, and N. Yoshikawa, \u201cDevelopment of the wideband cryoprobe for evaluating superconducting integrated circuits,\u201d IEICE Trans. Electron. (Japanese Edition), vol.J104-C, no.6, pp.193-201, 2021. DOI: 10.14923\/transelej.2020JCI0013 10.14923\/transelej.2020JCI0013","DOI":"10.14923\/transelej.2020JCI0013"},{"key":"37","doi-asserted-by":"publisher","unstructured":"[37] N. Takeuchi, T. Yamae, C.L. Ayala, H. Suzuki, and N. Yoshikawa, \u201cAn adiabatic superconductor 8-bit adder with 24 <i>k<\/i><sub>B<\/sub><i>T<\/i> energy dissipation per junction,\u201d Appl. Phys. Lett., vol.114, no.4, 042602, Jan. 2019. DOI: 10.1063\/1.5080753 10.1063\/1.5080753","DOI":"10.1063\/1.5080753"},{"key":"38","doi-asserted-by":"publisher","unstructured":"[38] Y. Yamazaki, N. Takeuchi, and N. Yoshikawa, \u201cA compact interface between adiabatic quantum-flux-parametron and rapid single-flux-quantum circuits,\u201d IEEE Trans. Appl. Supercond., vol.31, no.5, Article no. 1302705, Aug. 2021. DOI: 10.1109\/TASC.2021. 3072002 10.1109\/TASC.2021.3072002","DOI":"10.1109\/TASC.2021.3072002"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E105.C\/6\/E105.C_2021SEP0002\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,4]],"date-time":"2022-06-04T04:14:03Z","timestamp":1654316043000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E105.C\/6\/E105.C_2021SEP0002\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,1]]},"references-count":38,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2021sep0002","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,6,1]]},"article-number":"2021SEP0002"}}