{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T20:37:23Z","timestamp":1777495043668,"version":"3.51.4"},"reference-count":34,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2023,7,1]]},"DOI":"10.1587\/transele.2022cdp0004","type":"journal-article","created":{"date-parts":[[2022,12,18]],"date-time":"2022-12-18T22:10:20Z","timestamp":1671401420000},"page":"352-364","source":"Crossref","is-referenced-by-count":3,"title":["Write Variation &amp; Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM"],"prefix":"10.1587","volume":"E106.C","author":[{"given":"Shinsei","family":"YOSHIKIYO","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Naoko","family":"MISAWA","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kasidit","family":"TOPRASERTPONG","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shinichi","family":"TAKAGI","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chihiro","family":"MATSUI","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ken","family":"TAKEUCHI","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] N. 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Takagi, \u201cImproved ferroelectric\/semiconductor interface properties in Hf<sub>0.5<\/sub>Zr<sub>0.5<\/sub>O<sub>2<\/sub> ferroelectric FETs by low-temperature annealing,\u201d IEEE Electron Device Lett., vol.41, no.10, pp.1588-1591, 2020. 10.1109\/led.2020.3019265","DOI":"10.1109\/LED.2020.3019265"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E106.C\/7\/E106.C_2022CDP0004\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,12,3]],"date-time":"2023-12-03T05:54:39Z","timestamp":1701582879000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E106.C\/7\/E106.C_2022CDP0004\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7,1]]},"references-count":34,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2023]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2022cdp0004","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,7,1]]},"article-number":"2022CDP0004"}}