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Karl, \u201cA 23.6Mb\/mm<sup>2<\/sup> SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications,\u201d ISSCC Dig. Tech. Paper, San Francisco, CA, USA, pp.196-198, 2018. DOI: 10.1109\/ISSCC.2018.8310251 10.1109\/isscc.2018.8310251","DOI":"10.1109\/ISSCC.2018.8310251"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] Y.-W. Chiu, Y.-H. Hu, M.-H. Tu, J.-K. Zhao, Y.-H. Chu, S.-J. Jou, and C.-T. Chuang, \u201c40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist,\u201d in IEEE Trans. Circuits Syst. I, Reg. Papers, vol.61, no.9, pp.2578-2585, Sept. 2014, DOI: 10.1109\/TCSI.2014.2332267. 10.1109\/tcsi.2014.2332267","DOI":"10.1109\/TCSI.2014.2332267"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] K. Matsumoto, T. Hirose, Y. Osaki, N. Kuroki, and M. Numa, \u201cSubthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit,\u201d IEICE Trans. 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Chang, \u201c19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme,\u201d ISSCC Dig. Tech. Paper, San Francisco, CA, USA, pp.332-333, 2014. DOI: 10.1109\/ISSCC.2014.6757457 10.1109\/isscc.2014.6757457","DOI":"10.1109\/ISSCC.2014.6757457"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] S. Nalam and B.H. Calhoun, \u201c5T SRAM With Asymmetric Sizing for Improved Read Stability,\u201d IEEE J. of Solid-State Circuits, vol.46, no.10, pp.2431-2442, Oct. 2011. DOI: 10.1109\/JSSC.2011.2160812 10.1109\/jssc.2011.2160812","DOI":"10.1109\/JSSC.2011.2160812"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] J. Keane, J. Kulkarni, K.-H. Koo, S. Nalam, Z. Guo, E. Karl, and K. Zhang, \u201c17.2 5.6Mb\/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology,\u201d ISSCC Dig. Tech. Paper, San Francisco, CA, USA, pp.308-309, 2016. DOI: 10.1109\/ISSCC.2016.7418030 10.1109\/isscc.2016.7418030","DOI":"10.1109\/ISSCC.2016.7418030"},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] J.P. Kulkarni, J. Keane, K.-H. Koo, S. Nalam, Z. Guo, E. Karl, and K. Zhang, \u201c5.6 Mb\/mm<sup>2<\/sup> 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology,\u201d IEEE J. of Solid-State Circuits, vol.52, no.1, pp.229-239, Jan. 2017. DOI: 10.1109\/JSSC.2016.2607219 10.1109\/jssc.2016.2607219","DOI":"10.1109\/JSSC.2016.2607219"},{"key":"28","doi-asserted-by":"publisher","unstructured":"[28] M. Qazi, K. Stawiasz, L. Chang, and A.P. Chandrakasan, \u201cA 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS,\u201d IEEE J. of Solid-State Circuits, vol.46, no.1, pp.85-96, Jan. 2011. DOI: 10.1109\/JSSC.2010.2085970 10.1109\/jssc.2010.2085970","DOI":"10.1109\/JSSC.2010.2085970"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] D.-H. Jung, H. Jeong, T. Song, G. Kim, and S.-O. Jung, \u201cSource follower based single ended sense amplifier for large capacity SRAM,\u201d 2013 Int. SoC Design Conf. (ISOCC), Busan, Korea (South), pp.364-367, 2013. DOI: 10.1109\/ISOCC.2013.6864051 10.1109\/isocc.2013.6864051","DOI":"10.1109\/ISOCC.2013.6864051"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] M. Yabuuchi, Y. Tsukamoto, H. Fujiwara, M. Tanaka, S. Tanaka, and K. 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