{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T04:31:23Z","timestamp":1728534683079},"reference-count":35,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2023,6,1]]},"DOI":"10.1587\/transele.2022lhp0002","type":"journal-article","created":{"date-parts":[[2022,11,29]],"date-time":"2022-11-29T06:57:41Z","timestamp":1669705061000},"page":"312-320","source":"Crossref","is-referenced-by-count":0,"title":["An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture"],"prefix":"10.1587","volume":"E106.C","author":[{"given":"Ken","family":"NAKAMURA","sequence":"first","affiliation":[{"name":"NTT Device Innovation Center, NTT Corporation"},{"name":"Graduate School of Information Sciences Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuya","family":"OMORI","sequence":"additional","affiliation":[{"name":"NTT Device Innovation Center, NTT Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daisuke","family":"KOBAYASHI","sequence":"additional","affiliation":[{"name":"NTT Device Innovation Center, NTT Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koyo","family":"NITTA","sequence":"additional","affiliation":[{"name":"University of Aizu"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kimikazu","family":"SANO","sequence":"additional","affiliation":[{"name":"NTT Device Innovation Center, NTT Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masayuki","family":"SATO","sequence":"additional","affiliation":[{"name":"Graduate School of Information Sciences Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroe","family":"IWASAKI","sequence":"additional","affiliation":[{"name":"Graduate School of Information Sciences Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroaki","family":"KOBAYASHI","sequence":"additional","affiliation":[{"name":"Graduate School of Information Sciences Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] ISO\/IEC 13818-1\/2\/3 International Standard, Information Technology-Generic Coding of Moving Pictures and Associated Audio: Systems\/Visual\/Audio-, Nov. 1994."},{"key":"2","unstructured":"[2] ISO\/IEC 14496-10:2003, \u201cInformation technology-Coding of audio-visual objects-Part 10: Advanced Video Coding,\u201d Dec. 2003."},{"key":"3","unstructured":"[3] ISO\/IEC 23008-2:2013 \u201cInformation technology-High efficiency coding and media delivery in heterogeneous environments-Part 2: High efficiency video coding,\u201d Dec. 2013."},{"key":"4","unstructured":"[4] ISO\/IEC 23090-3:2021 \u201cInformation technology-Coded representation of immersive media-Part 3: Versatile video coding,\u201d Feb. 2021."},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] G.J. Sullivan, J.-R. Ohm, W.-J. Han, and T. Wiegand, \u201cOverview of the high efficiency video coding (HEVC) standard,\u201d IEEE Trans. Circuits Syst. Video Technol., vol.22, no.12, pp.1649-1668, Dec. 2012. 10.1109\/tcsvt.2012.2221191","DOI":"10.1109\/TCSVT.2012.2221191"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] B. Bross, Y.-K. Wang, Y. Ye, S. Liu, J. Chen, G.J. Sullivan, and J.-R. Ohm, \u201cOverview of the Versatile Video Coding (VVC) Standard and its Applications,\u201d IEEE Transactions on Circuits and Systems for Video Technology, vol.31, no.10, pp.3736-3764, Oct. 2021. 10.1109\/tcsvt.2021.3101953","DOI":"10.1109\/TCSVT.2021.3101953"},{"key":"7","unstructured":"[7] S.-F. Tsai, C.-T. Li, H.-H. Chen, P.-K. Tsung, K.-Y. Chen and L.-G. Chen, \u201cA 1062Mpixels\/s 8192\u00d74320p High Efficiency Video Coding (H.265) encoder chip,\u201d 2013 Symposium on VLSI Circuits, pp.C188-C189, 2013."},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] L.-F. Ding, W.-Y. Chen, P.-K. Tsung, T.-D. Chuang, H.-K. Chiu, Y.-H. Chen, P.-H. Hsiao, S.-Y. Chien, T.-C. Chen, P.-C. Lin, C.-Y. Chang, and L.-G. Chen, \u201cA 212MPixels\/s 4096\u00d72160p multiview video encoder chip for 3D\/quad HDTV applications,\u201d 2009 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, pp.154-155, 2009. 10.1109\/isscc.2009.4977354","DOI":"10.1109\/ISSCC.2009.4977354"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] M. Ikeda, et al., \u201cAn MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative,\u201d DATE' 99: Design, automation and test in Europe Conference and Exhibition, Jan. 1999.","DOI":"10.1145\/307418.307445"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] I. Iwasaki, J. Naganuma, K. Nitta, K. Nakamura, T. Yoshitome, M. Ogura, Y. Nakajima, Y. Tashiro, T. Onishi, M. Ikeda, and M. Endo, \u201cSingle-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond HDTV level,\u201d 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.2-7, 2003. 10.1109\/date.2003.1253796","DOI":"10.1109\/DATE.2003.1253796"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] K. Nitta, H. Iwasaki, T. Onishi, T. Sano, A. Sagata, Y. Nakajima, M. Inamori, R. Tanida, A. Shimizu, K. Nakamura, M. Ikeda, and J. Naganuma, \u201cAn H.264\/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures, \u201d IEICE Transactions on Electronics, vol.E95-C, no.4, pp.432-440, June 2012. 10.1587\/transele.e95.c.432","DOI":"10.1587\/transele.E95.C.432"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] T. Onishi, T. Sano, Y. Nishida, K. Yokohari, K. Nakamura, K. Nitta, K. Kawashima, J. Okamoto, N. Ono, A. Sagata, H. Iwasaki, M. Ikeda, and A. Shimizu, \u201cA Single-Chip 4K 60-fps 4:2:2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework with Scalability to 8K,\u201d IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.26, no.10, pp.1930-1938, June 2018. 10.1109\/tvlsi.2018.2842179","DOI":"10.1109\/TVLSI.2018.2842179"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] K. Nakamura, M. Ikeda, T. Yoshitome, and T. Ogura, \u201cGlobal rate control scheme for MPEG-2 HDTV parallel encoding system,\u201d Proceedings International Conference on Information Technology: Coding and Computing (Cat. no.PR00540), pp.195-200, 2000. 10.1109\/itcc.2000.844209","DOI":"10.1109\/ITCC.2000.844209"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] Y. Omori, T. Onishi, H. Iwasaki, and A. Shimizu, \u201cA 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K,\u201d IEEE Transactions on Multi-Scale Computing Systems, vol.4, no.4, pp.491-499, 2018. 10.1109\/tmscs.2018.2825320","DOI":"10.1109\/TMSCS.2018.2825320"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] Y. Omori, K. Nakamura, T. Onishi, D. Kobayashi, T. Osawa, and H. Iwasaki, \u201c4K 120fps HEVC Encoder with Multi-Chip Configuration,\u201d IEICE Transactions on Communications, vol.E104-B, no.7, pp.749-759, 2021. 10.1587\/transcom.2020cqp0004","DOI":"10.1587\/transcom.2020CQP0004"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] K. Nakamura, Y. Omori, D. Kobayashi, T. Osawa, T. Onishi, K. Nitta, H. Iwasaki, and A. Shimizu, \u201cLow Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture,\u201d 2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), pp.1-3, 2019. 10.1109\/coolchips.2019.8721335","DOI":"10.1109\/CoolChips.2019.8721335"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Y. Sugito, K. Iguchi, A. Ichigaya, K. Chida, S. Sakaida, H. Sakate, Y. Matsuda, Y. Kawahata, and N. Motoyama, \u201cHEVC\/H.265 Codec System and Transmission Experiments Aimed at 8K Broadcasting,\u201d The Best of IET and IBC 2015-2016, vol.7, pp.24-29, 2015. 10.1049\/ibc.2015.0051","DOI":"10.1049\/ibc.2015.0051"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] E. Nogues, D. Menard, and M. Pelcat, \u201cAlgorithmic-Level Approximate Computing Applied to Energy Efficient HEVC Decoding,\u201d IEEE Transactions on Emerging Topics in Computing, vol.7, no.1, pp.5-17, Jan.-March 2019. 10.1109\/tetc.2016.2593644","DOI":"10.1109\/TETC.2016.2593644"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] F. Qiao, N. Zhou, Y. Chen, and H. Yang, \u201cApproximate Computing in Chrominance Cache for Image\/Video Processing,\u201d 2015 IEEE International Conference on Multimedia Big Data, pp.180-183, 2015. 10.1109\/bigmm.2015.68","DOI":"10.1109\/BigMM.2015.68"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] W. El-Harouni, S. Rehman, B.S. Prabakaran, A. Kumar, R. Hafiz, and M. Shafique, \u201cEmbracing approximate computing for energy-efficient motion estimation in high efficiency video coding,\u201d Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp.1384-1389, 2017. 10.23919\/date.2017.7927209","DOI":"10.23919\/DATE.2017.7927209"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] Y. Fan, Q. Shang, and X. Zeng, \u201cIn-Block Prediction-Based Mixed Lossy and Lossless Reference Frame Recompression for Next-Generation Video Encoding,\u201d IEEE Transactions on Circuits and Systems for Video Technology, vol.25, no.1, pp.112-124, Jan. 2015. 10.1109\/tcsvt.2014.2329353","DOI":"10.1109\/TCSVT.2014.2329353"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] M. Budagavi and M. Zhou, \u201cVideo coding using compressed reference frames,\u201d 2008 IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.1165-1168, 2008. 10.1109\/icassp.2008.4517822","DOI":"10.1109\/ICASSP.2008.4517822"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] S. Zuo, M. Wang, and L. Xiao, \u201cA Cache Hardware Design for H.264 Encoder,\u201d 2012 Second International Conference on Instrumentation, Measurement, Computer, Communication and Control, pp.922-925, 2012. 10.1109\/imccc.2012.221","DOI":"10.1109\/IMCCC.2012.221"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] D. Woo, C. Rhee, and H.-J. Lee, \u201cA cache-aware motion estimation organization for a hardware-based H.264 encoder,\u201d IEEE Transactions on Consumer Electronics, vol.60, no.1, pp.83-91, Feb. 2014. 10.1109\/tce.2014.6780929","DOI":"10.1109\/TCE.2014.6780929"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] P.-K. Tsung, W.-Y. Chen, L.-F. Ding, S.-Y. Chien, and L.-G. Chen, \u201cCache-based integer motion\/disparity estimation for quad-HD H.264\/AVC and HD multiview video coding,\u201d 2009 IEEE International Conference on Acoustics, Speech and Signal Processing, pp.2013-2016, 2009. 10.1109\/icassp.2009.4960008","DOI":"10.1109\/ICASSP.2009.4960008"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] C.-Y. Tsai, C.-H. Chung, Y.-H. Chen, T.-C. Chen, and L.-G. Chen, \u201cLow Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264\/AVC Encoder System,\u201d 2007 IEEE International Conference on Acoustics, Speech and Signal Processing-ICASSP '07, pp.II-97-II-100, 2007. 10.1109\/icassp.2007.366181","DOI":"10.1109\/ICASSP.2007.366181"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] A. Martins, W. Penny, M. Weber, L. Agostini, M. Porto, D. Palomino, J. Mattos, and B. Zatt, \u201cConfigurable Cache Memory Architecture for Low-Energy Motion Estimation,\u201d 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, 2018. 10.1109\/iscas.2018.8351662","DOI":"10.1109\/ISCAS.2018.8351662"},{"key":"28","unstructured":"[28] Y. Kondo, et al., \u201cA Shared Cache Architecture for VVC Coding,\u201d 2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), pp.325, 2022."},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel, \u201cScratchpad memory: design alternative for cache on-chip memory in embedded systems,\u201d Proceedings of the Tenth International Symposium on Hardware\/Software Codesign. CODES 2002, pp.73-78, 2002. 10.1145\/774789.774805","DOI":"10.1145\/774789.774805"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] C.-Y. Chen, C.-T. Huang, Y.-H. Chen, and L.-G. Chen, \u201cLevel C+ data reuse scheme for motion estimation with corresponding coding orders,\u201d IEEE Transactions on Circuits and Systems for Video Technology, vol.16, no.4, pp.553-558, April 2006. 10.1109\/tcsvt.2006.871388","DOI":"10.1109\/TCSVT.2006.871388"},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] F.M. Sampaio, B. Zatt, M. Shafique, J. Henkel, and S. Bampi, \u201cHybrid Scratchpad Video Memory Architecture for Energy-Efficient Parallel HEVC,\u201d IEEE Transactions on Circuits and Systems for Video Technology, vol.29, no.10, pp.3046-3060, Oct. 2018. 10.1109\/tcsvt.2018.2870825","DOI":"10.1109\/TCSVT.2018.2870825"},{"key":"32","unstructured":"[32] ARIB STD-B32, Video Coding Audio Coding and Multiplexing Specifications for Digital Broadcasting, 2016."},{"key":"33","doi-asserted-by":"publisher","unstructured":"[33] N. Binkert, B. Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, and D.A. Wood, \u201cThe gem5 simulator,\u201d SIGARCH Comput. Archit. News, vol.39, no.2, pp.1-7, Aug. 2011. 10.1145\/2024716.2024718","DOI":"10.1145\/2024716.2024718"},{"key":"34","unstructured":"[34] G. Bj\u00f8ntegaard, \u201cCalculation of Average PSNR Differences between RD-curves\u201d VCEG-M33, 2001."},{"key":"35","unstructured":"[35] \u201cCommunicator Chip for Power-aware, Dependable, and High-performance Communication Link Using PCI Express: PEACH,\u201d SIC Technical reports, 2010-EMB-15, no.12, pp.1-6, 2020 (in Japanese)."}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E106.C\/6\/E106.C_2022LHP0002\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,9]],"date-time":"2024-10-09T17:26:53Z","timestamp":1728494813000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E106.C\/6\/E106.C_2022LHP0002\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,1]]},"references-count":35,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2023]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2022lhp0002","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"type":"print","value":"0916-8524"},{"type":"electronic","value":"1745-1353"}],"subject":[],"published":{"date-parts":[[2023,6,1]]},"article-number":"2022LHP0002"}}