{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,5]],"date-time":"2024-10-05T03:40:16Z","timestamp":1728099616937},"reference-count":16,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2024,10,1]]},"DOI":"10.1587\/transele.2023cts0001","type":"journal-article","created":{"date-parts":[[2024,4,15]],"date-time":"2024-04-15T22:16:47Z","timestamp":1713219407000},"page":"436-439","source":"Crossref","is-referenced-by-count":0,"title":["3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing"],"prefix":"10.1587","volume":"E107.C","author":[{"given":"Fuyuki","family":"KIHARA","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo"}]},{"given":"Chihiro","family":"MATSUI","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo"}]},{"given":"Ken","family":"TAKEUCHI","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] P. Kanerva, \u201cHyperdimensional Computing: An introduction to computing in distributed representation with high-dimensional random vectors,\u201d Cognitive Computation, vol.1, no.2, pp.139-159, 2009. DOI: 10.1007\/s12559-009-9009-8 10.1007\/s12559-009-9009-8","DOI":"10.1007\/s12559-009-9009-8"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] D. Kleyko, D.A. Rachkovskij, E. Osipov, and A. Rahimi, \u201cA survey on hyperdimensional computing aka vector symbolic architectures, Part I: Models and data transformations,\u201d ACM Computing Surveys, vol.55, no.6, Article No.130, 2022. DOI: 10.1145\/3538531 10.1145\/3538531","DOI":"10.1145\/3538531"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] E. Hassan, Y. Halawani, B. Mohammad, and H. Saleh, \u201cHyper-dimensional computing challenges and opportunities for AI applications,\u201d IEEE Access, vol.10, pp.97651-97664, 2022. DOI: 10.1109\/ACCESS.2021.3059762 10.1109\/ACCESS.2021.3059762","DOI":"10.1109\/ACCESS.2021.3059762"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] C. Matsui, E. Kobayashi, N. Misawa, and K. Takeuchi, \u201cComprehensive analysis on error-robustness of FeFET computation-in-memory for hyperdimensional computing,\u201d Japanese Journal of Applied Physics (JJAP), vol.62, no.SC, pp.SC1053-1-SC1053-13, Feb. 2023. 10.35848\/1347-4065\/acb1b8","DOI":"10.35848\/1347-4065\/acb1b8"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] H. Li, T.F. Wu, A. Rahimi, K.-S. Li, M. Rusch, C.-H. Lin, J.-L. Hsu, M.M. Sabry, S.B. Eryilmaz, J. Sohn, W.-C. Chiu, M.-C. Chen, T.-T. Wu, J.-M. Shieh, W.-K. Yeh, J.M. Rabaey, S. Mitra, and H.-S.P. Wong, \u201cHyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition,\u201d 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp.16.1.1-16.1.4, 2016. DOI: 10.1109\/IEDM.2016.7838428 10.1109\/IEDM.2016.7838428","DOI":"10.1109\/IEDM.2016.7838428"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] G. Karunaratne, M. Le Gallo, G. Cherubini, L. Benini, A. Rahimi, and A. Sebastian, \u201cIn-memory hyperdimensional computing,\u201d Nature Electronics, vol.3, pp.327-337, 2020. DOI: 10.1038\/s41928-020-0410-3 10.1038\/s41928-020-0410-3","DOI":"10.1038\/s41928-020-0410-3"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] A. Kazemi, M.M. Sharifi, Z. Zou, M. Niemier, X.S. Hu, and M. Imani, \u201cMIMHD: Accurate and efficient hyperdimensional inference using multi-bit in-memory computing,\u201d 2021 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED), Boston, MA, USA, pp.1-6, 2021. 10.1109\/ISLPED52811.2021.9502498","DOI":"10.1109\/ISLPED52811.2021.9502498"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] P.-K. Hsu and S. Yu, \u201cIn-memory 3D NAND flash hyperdimensional computing engine for energy-efficient SARS-CoV-2 genome sequencing,\u201d 2022 IEEE International Memory Workshop (IMW), Dresden, Germany, pp.1-4, 2022. 10.1109\/IMW52921.2022.9779291","DOI":"10.1109\/IMW52921.2022.9779291"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] T. Dubreuil, P. Amari, S. Barraud, J. Lacord, E. Esmanhotto, V. Meli, S. Martin, N. Castellani, B. Previtali, and F. Andrieu, \u201cA novel 3D 1T1R RRAM architecture for memory-centric hyperdimensional computing,\u201d 2022 IEEE International Memory Workshop (IMW), Dresden, Germany, pp.1-4, 2022. 10.1109\/IMW52921.2022.9779306","DOI":"10.1109\/IMW52921.2022.9779306"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] T. Dubreuil, S. Barraud, B. Previtali, S. Martinie, J. Lacord, S. Martin, N. Castellani, A. Anotta, and F. Andrieu, \u201cFabrication of low-power RRAM for stateful hyperdimensional computing,\u201d 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA\/VLSI-DAT), HsinChu, Taiwan, pp.1-2, 2023. DOI: 10.1109\/VLSI-TSA\/VLSI-DAT57221.2023.10134182 10.1109\/VLSI-TSA\/VLSI-DAT57221.2023.10134182","DOI":"10.1109\/VLSI-TSA\/VLSI-DAT57221.2023.10134182"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] S. Mittal, \u201cA survey of ReRAM-based architectures for processing-in-memory and neural networks,\u201d Machine Learning and Knowledge Extraction, vol.1, no.1, pp.75-114, 2019. DOI: 10.3390\/make1010005 10.3390\/make1010005","DOI":"10.3390\/make1010005"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] Y. Chen, \u201cReRAM: History, status, and future,\u201d IEEE Trans. Electron Devices, vol.67, no.4, pp.1420-1433, April 2020. DOI: 10.1109\/TED.2019.2961505 10.1109\/TED.2019.2961505","DOI":"10.1109\/TED.2019.2961505"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] A. Yamada, N. Misawa, C. Matsui, and K. Takeuchi, \u201cReRAM CiM fluctuation pattern classification by CNN trained on artificially created dataset,\u201d 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, pp.1-6, 2023. 10.1109\/IRPS48203.2023.10118305","DOI":"10.1109\/IRPS48203.2023.10118305"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] D. Takashima, I. Kunishima, M. Noguchi, and S. Takagi, \u201cHigh-density chain ferroelectric random-access memory (CFRAM),\u201d Symposium on VLSI Circuit, pp.83-84, 1997. 10.1109\/VLSIC.1997.623818","DOI":"10.1109\/VLSIC.1997.623818"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] M. Kinoshita, Y. Sasago, H. Minemura, Y. Anzai, M. Tai, Y. Fujisaki, S. Kusaba, T. Morimoto, T. Takahama, T. Mine, A. Shima, Y. Yonamoto, and T. Kobayashi, \u201cScalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes,\u201d 2012 Symposium on VLSI Technology, pp.35-36, 2012. 10.1109\/VLSIT.2012.6242448","DOI":"10.1109\/VLSIT.2012.6242448"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, \u201cLeakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,\u201d Proc. IEEE, vol.91, no.2, pp.305-327, Feb. 2003. DOI: 10.1109\/JPROC.2002.808156 10.1109\/JPROC.2002.808156","DOI":"10.1109\/JPROC.2002.808156"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E107.C\/10\/E107.C_2023CTS0001\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,5]],"date-time":"2024-10-05T03:24:16Z","timestamp":1728098656000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E107.C\/10\/E107.C_2023CTS0001\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,1]]},"references-count":16,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2023cts0001","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"type":"print","value":"0916-8524"},{"type":"electronic","value":"1745-1353"}],"subject":[],"published":{"date-parts":[[2024,10,1]]},"article-number":"2023CTS0001"}}