{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T00:17:28Z","timestamp":1725754648557},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"9","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2024,9,1]]},"DOI":"10.1587\/transele.2023ecp5049","type":"journal-article","created":{"date-parts":[[2024,4,8]],"date-time":"2024-04-08T22:14:24Z","timestamp":1712614464000},"page":"245-254","source":"Crossref","is-referenced-by-count":0,"title":["Computer-Aided Design of Cross-Voltage-Domain Energy-Optimized Tapered Buffers"],"prefix":"10.1587","volume":"E107.C","author":[{"given":"Zhibo","family":"CAO","sequence":"first","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University"}]},{"given":"Pengfei","family":"HAN","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University"}]},{"given":"Hongming","family":"LYU","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University"},{"name":"Shanghai Engineering Research Center of Energy Efficient and Custom AI IC"},{"name":"State Key Laboratory of Advanced Medical Materials and Devices, ShanghaiTech University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] G. Tochou, A. Cathelin, A. Frapp\u00e9, A. Kaiser, and J. Rabaey, \u201cImpact of forward body-biasing on ultra-low voltage switched-capacitor RF power amplifier in 28 nm FD-SOI,\u201d IEEE Transactions on Circuits and Systems II: Express Briefs, vol.69, no.1, pp.50-54, 2021. 10.1109\/tcsii.2021.3088996","DOI":"10.1109\/TCSII.2021.3088996"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] A. Abuelnasr, M. Amer, M. Ali, A. Hassan, B. Gosselin, A. Ragab, and Y. Savaria, \u201cDelay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers,\u201d IEEE Transactions on Circuits and Systems I: Regular Papers, vol.70, no.4, pp.1555-1565, 2023. 10.1109\/tcsi.2022.3232074","DOI":"10.1109\/TCSI.2022.3232074"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] H. Zhang, S. Karmakar, L.J. Breems, Q. Sandifort, M. Berkhout, K.A.A. Makinwa, and Q. Fan, \u201cA high-linearity and low-EMI multilevel class-D amplifier,\u201d IEEE Journal of Solid-State Circuits, vol.56, no.4, pp.1176-1185, 2020. 10.1109\/jssc.2020.3043815","DOI":"10.1109\/JSSC.2020.3043815"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] R.J. Bootsman, et al., \u201cHigh-power digital transmitters for wireless infrastructure applications (a feasibility study),\u201d IEEE Transactions on Microwave Theory and Techniques, vol.70, no.5, pp.2835-2850, 2022.","DOI":"10.1109\/TMTT.2022.3153000"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] A. Mishra and V. De Smedt, \u201cA novel hybrid buck-boost converter topology for Li-ion batteries with increased efficiency,\u201d 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.1-4, IEEE, 2020. 10.1109\/icecs49266.2020.9294872","DOI":"10.1109\/ICECS49266.2020.9294872"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] H. Ma, G. Namgoong, E. Choi, and F. Bien, \u201cInstantaneous power consuming level-shifter for improving power conversion efficiency of buck converter,\u201d IEEE Transactions on Circuits and Systems II: Express Briefs, vol.66, no.7, pp.1207-1211, 2018. 10.1109\/tcsii.2018.2878042","DOI":"10.1109\/TCSII.2018.2878042"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] P.A.E. Divino, M.P. Prunes, and K.O. Maglinte, \u201cSingle-Inductor Multiple-Output (SIMO) Boost DC-DC Converter using Ripple-Based Control for Ultra-Low Power Indoor Light Energy Harvesting Applications,\u201d 2019 IEEE 11th International Conference on Humanoid, Nanotechnology, Information Technology, Communica-tion and Control, Environment, and Management (HNICEM), pp.1-6, IEEE, 2019. 10.1109\/hnicem48295.2019.9072862","DOI":"10.1109\/HNICEM48295.2019.9072862"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] M.W. Kim and J.J. Kim, \u201cA PWM\/PFM dual-mode DC-DC buck converter with load-dependent efficiency-controllable scheme for multi-purpose IoT applications,\u201d Energies, vol.14, no.4, p.960, 2021. 10.3390\/en14040960","DOI":"10.3390\/en14040960"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] S. Ma and P. Franzon, \u201cEnergy control and accurate delay estimation in the design of CMOS buffers,\u201d IEEE Journal of Solid-State Circuits, vol.29, no.9, pp.1150-1153, 1994. 10.1109\/4.309914","DOI":"10.1109\/4.309914"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] C.W. Kang, S. Abbaspour, and M. Pedram, \u201cBuffer sizing for minimum energy-delay product by using an approximating polynomial,\u201d Proceedings of the 13th ACM Great Lakes symposium on VLSI, pp.112-115, 2003. 10.1145\/764825.764838","DOI":"10.1145\/764808.764838"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] B.S. Cherkauer and E.G. Friedman, \u201cA unified design methodology for CMOS tapered buffers,\u201d IEEE Transactions on Very Large Scale Integration Systems, vol.3, no.1, pp.99-111, 1995. 10.1109\/92.365457","DOI":"10.1109\/92.365457"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] S.R. Vemuru and A.R. Thorbjornsen, \u201cVariable-taper CMOS buffers,\u201d IEEE Journal of Solid-State Circuits, vol.26, no.9, pp.1265-1269, 1991. 10.1109\/4.84943","DOI":"10.1109\/4.84943"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] H. Wang, M. Miranda, A. Papanikolaou, F. Catthoor, and W. Dehaene, \u201cVariable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs,\u201d IEEE Transactions on Very Large Scale Integration Systems, vol.13, no.10, pp.1127-1135, 2005. 10.1109\/tvlsi.2005.859480","DOI":"10.1109\/TVLSI.2005.859480"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] J.-S. Choi and K. Lee, \u201cDesign of CMOS tapered buffer for minimum power-delay product,\u201d IEEE Journal of Solid-State Circuits, vol.29, no.9, pp.1142-1145, 1994. 10.1109\/4.309912","DOI":"10.1109\/4.309912"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] H.J.M. Veendrick, \u201cShort-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,\u201d IEEE Journal of Solid-State Circuits, vol.19, no.4, pp.468-473, 1984. 10.1109\/jssc.1984.1052168","DOI":"10.1109\/JSSC.1984.1052168"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] S. Turgis and D. Auvergne, \u201cA novel macromodel for power estimation in CMOS structures,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, no.11, pp.1090-1098, 1998. 10.1109\/43.736183","DOI":"10.1109\/43.736183"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] A.J. Stratakos, S.R. Sanders, and R.W. Brodersen, \u201cA low-voltage CMOS DC-DC converter for a portable battery-operated system,\u201d Proceedings of 1994 Power Electronics Specialist Conference-PESC&apos;94, vol.1, pp.619-626, IEEE, 1994. 10.1109\/pesc.1994.349672","DOI":"10.1109\/PESC.1994.349672"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] V. Kursun, S.G. Narendra, V.K. De, and E.G. Friedman, \u201cLow-voltage-swing monolithic dc-dc conversion,\u201d IEEE Transactions on Circuits Systems II: Express Briefs, vol.51, no.5, pp.241-248, 2004. 10.1109\/tcsii.2004.827557","DOI":"10.1109\/TCSII.2004.827557"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, W.G. Dunford, and P.R. Palmer, \u201cA fully integrated 660 MHz low-swing energy-recycling DC-DC converter,\u201d IEEE Transactions on Power Electronics, vol.24, no.6, pp.1475-1485, 2009. 10.1109\/tpel.2009.2013624","DOI":"10.1109\/TPEL.2009.2013624"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] F. Frustaci, P. Corsonello, and M. Alioto, \u201cTapered-V TH CMOS buffer design for improved energy efficiency in deep nanometer technology,\u201d 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.2075-2078, IEEE, 2011. 10.1109\/iscas.2011.5938006","DOI":"10.1109\/ISCAS.2011.5938006"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] S. Liu, S.O. Memik, and Y.I. Ismail, \u201cA comprehensive tapered buffer optimization algorithm for unified design metrics,\u201d 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.2277-2280, IEEE, 2011. 10.1109\/iscas.2011.5938056","DOI":"10.1109\/ISCAS.2011.5938056"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] W.T. Overeem, M.S.O. Alink, and B. Nauta, \u201cInverter Chain Buffer Optimization for N-path Filter Switch Drivers and Validation through Simulations in 22nm FD-SOI Technology,\u201d 2023 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, IEEE, 2023. 10.1109\/iscas46773.2023.10181574","DOI":"10.1109\/ISCAS46773.2023.10181574"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] S. Dutta, S.S.M. Shetti, and S.L. Lusky, \u201cA comprehensive delay model for CMOS inverters,\u201d IEEE Journal of Solid-State Circuits, vol.30, no.8, pp.864-871, 1995. 10.1109\/4.400428","DOI":"10.1109\/4.400428"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] P. Maurine, M. Rezzoug, N. Azemard, and D. Auvergne, \u201cTransition time modeling in deep submicron CMOS,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.21, no.11, pp.1352-1363, 2002. 10.1109\/tcad.2002.804088","DOI":"10.1109\/TCAD.2002.804088"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] S.R. Vemuru and N. Scheinberg, \u201cShort-circuit power dissipation estimation for CMOS logic gates,\u201d IEEE Transactions on Circuits Systems I: Fundamental Theory and Applications, vol.41, no.11, pp.762-765, 1994. 10.1109\/81.331533","DOI":"10.1109\/81.331533"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] T. Tanzawa, \u201cOn-chip high-voltage generator design,\u201d Springer, 2013. 10.1007\/978-1-4614-3849-6","DOI":"10.1007\/978-1-4614-3849-6"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] S. Turgis, N. Azemard, and D. Auvergne, \u201cExplicit evaluation of short circuit power dissipation for CMOS logic structures,\u201d Proceedings of the 1995 International Symposium on Low Power Design, pp.129-134, 1995. 10.1145\/224081.224104","DOI":"10.1145\/224081.224104"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] A. Hirata, H. Onodera, and K. Tamaru, \u201cEstimation of short-circuit power dissipation and its influence on propagation delay for static CMOS gates,\u201d 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96, vol.4, pp.751-754, IEEE, 1996. 10.1109\/iscas.1996.542133","DOI":"10.1109\/ISCAS.1996.542133"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] L. Bisdounis, S. Nikolaidis, and O. Loufopavlou, \u201cPropagation delay and short-circuit power dissipation modeling of the CMOS inverter,\u201d IEEE Transactions on Circuits and Systems I: Fundamental theory and applications, vol.45, no.3, pp.259-270, 1998. 10.1109\/81.662699","DOI":"10.1109\/81.662699"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] T. Sakurai and A.R. Newton, \u201cAlpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,\u201d IEEE Journal of Solid-State Circuits, vol.25, no.2, pp.584-594, 1990. 10.1109\/4.52187","DOI":"10.1109\/4.52187"},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] D. Auvergne, J.M. Daga, and M. Rezzoug, \u201cSignal transition time effect on CMOS delay evaluation,\u201d IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol.47, no.9, pp.1362-1369, 2000. 10.1109\/81.883331","DOI":"10.1109\/81.883331"},{"key":"32","unstructured":"[32] J.M. Rabaey, A.P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, Prentice Hall, Englewood Cliffs, 2002."},{"key":"33","doi-asserted-by":"publisher","unstructured":"[33] K. Nose and T. Sakurai, \u201cAnalysis and future trend of short-circuit power,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, no.9, pp.1023-1030, 2000. 10.1109\/43.863642","DOI":"10.1109\/43.863642"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E107.C\/9\/E107.C_2023ECP5049\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T03:23:51Z","timestamp":1725679431000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E107.C\/9\/E107.C_2023ECP5049\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,1]]},"references-count":33,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2023ecp5049","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"type":"print","value":"0916-8524"},{"type":"electronic","value":"1745-1353"}],"subject":[],"published":{"date-parts":[[2024,9,1]]},"article-number":"2023ECP5049"}}