{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,8]],"date-time":"2024-12-08T05:03:58Z","timestamp":1733634238485,"version":"3.30.1"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2024,12,1]]},"DOI":"10.1587\/transele.2023ecp5051","type":"journal-article","created":{"date-parts":[[2024,5,7]],"date-time":"2024-05-07T22:11:14Z","timestamp":1715119874000},"page":"545-556","source":"Crossref","is-referenced-by-count":0,"title":["Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM"],"prefix":"10.1587","volume":"E107.C","author":[{"given":"Yihan","family":"ZHU","sequence":"first","affiliation":[{"name":"Graduate School of Information, Production and Systems, Waseda University"}]},{"given":"Takashi","family":"OHSAWA","sequence":"additional","affiliation":[{"name":"Graduate School of Information, Production and Systems, Waseda University"}]}],"member":"532","reference":[{"doi-asserted-by":"crossref","unstructured":"[1] V. Sze, Y.-H. Chen, T.-J. Yang, and J.S. Emer, Efficient Processing of Deep Neural Networks, Morgan &amp; Claypool Publishers, 2020. 10.1007\/978-3-031-01766-7","key":"1","DOI":"10.1007\/978-3-031-01766-7_2"},{"doi-asserted-by":"crossref","unstructured":"[2] N. Zheng and P. Mazumder, Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design, John Wiley &amp; Sons Ltd., 2019. 10.1002\/9781119507369","key":"2","DOI":"10.1002\/9781119507369"},{"doi-asserted-by":"publisher","unstructured":"[3] C. Yu, T. Yoo, K.T.C. Chai, T.T.-H. Kim, and B. Kim, \u201cA 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks,\u201d IEEE J. Solid-State Circuits, vol.57, no.11, pp.3466-3476, Nov. 2022. 10.1109\/jssc.2022.3162602","key":"3","DOI":"10.1109\/JSSC.2022.3162602"},{"doi-asserted-by":"publisher","unstructured":"[4] Z. Chen, Z. Yu, Q. Jin, Y. He, J. Wang, S. Lin, D. Li, Y. Wang, and K. Yang, \u201cCAP-RAM: A charge-domain in-memory computing 6T-SRAM for accurate and precision-programmable CNN inference,\u201d IEEE J. Solid-State Circuits, vol.56, no.6, pp.1924-1935, June 2021. 10.1109\/jssc.2021.3056447","key":"4","DOI":"10.1109\/JSSC.2021.3056447"},{"doi-asserted-by":"publisher","unstructured":"[5] H. Kim, T. Yoo, T.T.-H. Kim, and B. Kim, \u201cColonnade: A reconfigurable SRAM-based digital bit-serial compute-in-memory macro for processing neural networks,\u201d IEEE J. Solid-State Circuits, vol.56, no.7, pp.2221-2233, July 2021. 10.1109\/jssc.2021.3061508","key":"5","DOI":"10.1109\/JSSC.2021.3061508"},{"doi-asserted-by":"publisher","unstructured":"[6] Z. Lin, H. Zhan, Z. Chen, C. Peng, X. Wu, W. Lu, Q. Zhao, X. Li, and J. Chen, \u201cCascade current mirror to improve linearity and consistency in SRAM in-memory computing,\u201d IEEE J. Solid-State Circuits, vol.56, no.8, pp.2550-2562, Aug. 2021. 10.1109\/jssc.2021.3063719","key":"6","DOI":"10.1109\/JSSC.2021.3063719"},{"doi-asserted-by":"publisher","unstructured":"[7] H. Valavi, P.J. Ramadge, E. Nestler, and N. Verma, \u201cA 64-tile 2.4-Mb in-memory-computing CNN accelerator employing charge-domain compute,\u201d IEEE J. Solid-State Circuits, vol.54, no.6, pp.1789-1799, June 2019. 10.1109\/jssc.2019.2899730","key":"7","DOI":"10.1109\/JSSC.2019.2899730"},{"doi-asserted-by":"publisher","unstructured":"[8] C.-J. Jhang, C.-X. Xue, J.-M. Hung, F.-C. Chang, and M.-F. Chang, \u201cChallenges and trends of SRAM-based computing-in-memory for AI edge devices,\u201d IEEE Trans. Circuits Syst. I: Regul. Pap., vol.68, no.5, pp.1773-1786, May 2021. 10.1109\/tcsi.2021.3064189","key":"8","DOI":"10.1109\/TCSI.2021.3064189"},{"doi-asserted-by":"publisher","unstructured":"[9] Y. Zhang, L. Xu, Q. Dong, J. Wang, D. Blaauw, and D. Sylvester, \u201cRecryptor: A reconfigurable cryptographic cortex-M0 processor with in-memory and near-memory computing for IoT security,\u201d IEEE J. Solid-State Circuits, vol.53, no.4, pp.995-1005, April 2018. 10.1109\/jssc.2017.2776302","key":"9","DOI":"10.1109\/JSSC.2017.2776302"},{"doi-asserted-by":"crossref","unstructured":"[10] J. Wang, X. Wang, C. Eckert, A. Subramaniyan, R. Das, D. Blaauw, and D. Sylvester, \u201cA compute SRAM with bit-serial integer\/floating-point operations for programmable in-memory vector acceleration,\u201d International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp.224-226, Feb. 2019. 10.1109\/isscc.2019.8662419","key":"10","DOI":"10.1109\/ISSCC.2019.8662419"},{"doi-asserted-by":"publisher","unstructured":"[11] A. Biswas and A.P. Chandrakasan, \u201cCONV-SRAM: An energy-efficient SRAM with in-memory dot-product computation for low-power convolutional neural networks,\u201d IEEE J. Solid-State Circuits, vol.54, no.1, pp.217-230, Jan. 2019. 10.1109\/jssc.2018.2880918","key":"11","DOI":"10.1109\/JSSC.2018.2880918"},{"doi-asserted-by":"publisher","unstructured":"[12] K. Shin, W. Choi, and J. Park, \u201cHalf-select free bit-line sharing 9T SRAM for reliable supply voltage scaling,\u201d IEEE Trans. Circuits Syst. I: Regul. Pap., vol 64, no.8, pp.2036-2048, Aug. 2017. 10.1109\/tcsi.2017.2691354","key":"12","DOI":"10.1109\/TCSI.2017.2691354"},{"doi-asserted-by":"crossref","unstructured":"[13] Z. Jiang, S. Yin, M. Seok, and J.-s. Seo, \u201cXNOR-SRAM: In-memory computing SRAM macro for binary\/ternary deep neural networks,\u201d Symp. VLSI Tech. Dig. Tech. Papers, pp.173-174, June 2018. 10.1109\/vlsit.2018.8510687","key":"13","DOI":"10.1109\/VLSIT.2018.8510687"},{"doi-asserted-by":"crossref","unstructured":"[14] H. Valavi, P.J. Ramadge, E. Nestler, and N. Verma, \u201cA mixed-signal binarized convolutional-neural-network accelerator integrating dense weight storage and multiplication for reduced data movement,\u201d Symp. VLSI Circuits Dig. Tech. Papers, pp.141-142, June 2018. 10.1109\/vlsic.2018.8502421","key":"14","DOI":"10.1109\/VLSIC.2018.8502421"},{"doi-asserted-by":"publisher","unstructured":"[15] K. Noda, K. Matsui, K. Takeda, and N. Nakamura, \u201cA loadless CMOS four-transistor SRAM cell in a 0.18-\u03bcm logic technology,\u201d IEEE Trans. Electron Devices, vol.48, no.12, pp.2851-2855, Dec. 2001. 10.1109\/16.974716","key":"15","DOI":"10.1109\/16.974716"},{"doi-asserted-by":"crossref","unstructured":"[16] K. Imai, K. Yamaguchi, N. Kimizuka, H. Onishi, T. Kudo, A. Ono, K. Noda, Y. Goto, H. Fujii, M. Ikeda, K. Kazama, S. Maruyama, T. Kuwata, and T. Horiuchi, \u201cA 0.13-\u03bcm CMOS technology integrating high-speed and low-power\/high-density devices with two different well\/channel structures,\u201d IEDM Tech. Dig., pp.667-670, Dec. 1999. 10.1109\/iedm.1999.824240","key":"16","DOI":"10.1109\/IEDM.1999.824240"},{"doi-asserted-by":"publisher","unstructured":"[17] K. Noda, K. Takeda, K. Matsui, S. Masuoka, H. Kawamoto, N. Ikezawa, Y. Aimoto, N. Nakamura, T. Iwasaki, H. Toyoshima, and T. Horiuchi, \u201cAn ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield,\u201d IEEE J. Solid-State Circuits, vol.36, no.3, pp.510-515, March 2001. 10.1109\/4.910490","key":"17","DOI":"10.1109\/4.910490"},{"doi-asserted-by":"publisher","unstructured":"[18] Y. Zhu and T. Ohsawa, \u201cA loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters,\u201d Jpn. J. Appl. Phys., vol.61, SC1053, 2022. 10.35848\/1347-4065\/ac44ce","key":"18","DOI":"10.35848\/1347-4065\/ac44ce"},{"doi-asserted-by":"publisher","unstructured":"[19] Y. Zhu and T. Ohsawa, \u201cA gate leakage current-powered loadless 4T SRAM with immunity against random dopant fluctuation and surface roughness in silicon-silicon dioxide interface,\u201d Jpn. J. Appl. Phys., vol.62, SC1004, 2023. 10.35848\/1347-4065\/aca33b","key":"19","DOI":"10.35848\/1347-4065\/aca33b"},{"doi-asserted-by":"crossref","unstructured":"[20] Y. Zhu and T. Ohsawa, \u201cA bit-line disturb free loadless 4T SRAM using gate leakage current for sustaining data with high immunity against process variations,\u201d Extended Abstracts of the 2021 International Conference on Solid State Devices and Materials (SSDM), pp.678-679, Sept. 2021. 10.7567\/ssdm.2021.l-1-05","key":"20","DOI":"10.7567\/SSDM.2021.L-1-05"},{"doi-asserted-by":"crossref","unstructured":"[21] Y. Zhu and T. Ohsawa, \u201cA loadless 4T SRAM cell powered by gate leakage current and tolerant of random dopant fluctuation and surface roughness at Si-SiO<sub>2<\/sub> interface,\u201d Extended Abstracts of the 2021 International Conference on Solid State Devices and Materials (SSDM), pp.625-626, Sept. 2022. 10.7567\/ssdm.2022.j-10-04","key":"21","DOI":"10.7567\/SSDM.2022.J-10-04"},{"doi-asserted-by":"publisher","unstructured":"[22] E. Seevinck, P.J. van Beers, and H. Ontrop, \u201cCurrent-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM&apos;s,\u201d IEEE J. Solid-State Circuits, vol.26, no.4, pp.525-536, April 1991. 10.1109\/4.75050","key":"22","DOI":"10.1109\/4.75050"},{"unstructured":"[23] N. Shibata, \u201cCurrent sense amplifiers for low-voltage memories,\u201d IEICE Trans. Electron., vol.E79-C, no.8, pp.1120-1130, Aug. 1996.","key":"23"},{"unstructured":"[24] B. Wicht, Current Sense Amplifiers for Embedded SRAM in High-Performance System-on-a-Chip Designs, Springer-Verlag, Berlin, 2003. 10.1007\/978-3-662-06442-9","key":"24"},{"doi-asserted-by":"crossref","unstructured":"[25] A. Nguyen, K. Pham, D. Ngo, T. Ngo and L. Pham, \u201cAn analysis of state-of-the-art activation functions for supervised deep neural network\u201d International Conference on System Science and Engineering, pp.215-220, 2021. 10.1109\/icsse52999.2021.9538437","key":"25","DOI":"10.1109\/ICSSE52999.2021.9538437"},{"doi-asserted-by":"publisher","unstructured":"[26] Z. Chen and T. Ohsawa, \u201cA low-cost training method of ReRAM inference accelerator chips for binarized neural networks to recover accuracy degradation due to statistical variabilities,\u201d IEICE Trans. Electron., vol.E105-C, no.8, pp.375-384, Aug. 2022. 10.1587\/transele.2021ecp5040","key":"26","DOI":"10.1587\/transele.2021ECP5040"},{"doi-asserted-by":"crossref","unstructured":"[27] R.T. Greenway, K. Jeong, A.B. Kahng, C.-H. Park, and J.S. Petersen, \u201c32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography,\u201d Proc. SPIE, vol.7122, pp.71221L-1-71221L-12, Oct. 2008. 10.1117\/12.801883","key":"27","DOI":"10.1117\/12.801883"},{"doi-asserted-by":"publisher","unstructured":"[28] S. Yin, Z. Jiang, J.-S. Seo, and M. Seok, \u201cXNOR-SRAM: In-memory computing SRAM macro for binary\/ternary deep neural networks,\u201d IEEE J. Solid-State Circuits, vol.55, no.6, pp.1733-1743, June 2020. 10.1109\/jssc.2019.2963616","key":"28","DOI":"10.1109\/JSSC.2019.2963616"},{"doi-asserted-by":"crossref","unstructured":"[29] C. Yu, T. Yoo, T.T.-H. Kim, K.C.T. Chuan, and B. Kim, \u201cA 16K current-based 8T SRAM compute-in-memory macro with decoupled read\/write and 1-5bit column ADC,\u201d 2020 IEEE Custom Integrated Circuits Conference (CICC), March 2020. 10.1109\/cicc48029.2020.9075883","key":"29","DOI":"10.1109\/CICC48029.2020.9075883"},{"doi-asserted-by":"publisher","unstructured":"[30] A. Stillmaker and B. Baas, \u201cScaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm,\u201d Integration, vol.58, pp.74-81, 2017. 10.1016\/j.vlsi.2017.02.002","key":"30","DOI":"10.1016\/j.vlsi.2017.02.002"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E107.C\/12\/E107.C_2023ECP5051\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,7]],"date-time":"2024-12-07T03:22:06Z","timestamp":1733541726000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E107.C\/12\/E107.C_2023ECP5051\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,1]]},"references-count":30,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2023ecp5051","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"type":"print","value":"0916-8524"},{"type":"electronic","value":"1745-1353"}],"subject":[],"published":{"date-parts":[[2024,12,1]]},"article-number":"2023ECP5051"}}