{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T04:10:39Z","timestamp":1717215039847},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2024,6,1]]},"DOI":"10.1587\/transele.2023lhp0001","type":"journal-article","created":{"date-parts":[[2023,11,23]],"date-time":"2023-11-23T22:11:48Z","timestamp":1700777508000},"page":"155-162","source":"Crossref","is-referenced-by-count":0,"title":["A 0.13mJ\/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA"],"prefix":"10.1587","volume":"E107.C","author":[{"given":"Dongzhu","family":"LI","sequence":"first","affiliation":[{"name":"Graduate School of Engineering, The University of Tokyo"}]},{"given":"Zhijie","family":"ZHAN","sequence":"additional","affiliation":[{"name":"Graduate School of Engineering, The University of Tokyo"}]},{"given":"Rei","family":"SUMIKAWA","sequence":"additional","affiliation":[{"name":"Graduate School of Engineering, The University of Tokyo"}]},{"given":"Mototsugu","family":"HAMADA","sequence":"additional","affiliation":[{"name":"Graduate School of Engineering, The University of Tokyo"}]},{"given":"Atsutake","family":"KOSUGE","sequence":"additional","affiliation":[{"name":"Graduate School of Engineering, The University of Tokyo"}]},{"given":"Tadahiro","family":"KURODA","sequence":"additional","affiliation":[{"name":"Graduate School of Engineering, The University of Tokyo"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] K. Hirose, J. Yu, K. Ando, \u00c1.L. Garc\u00eda-Arias, J. Suzuki, T. Van Chu, K. Kawamura, and M. Motomura, \u201cHiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS\/W for CIFAR-100 and ImageNet,\u201d IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, San Francisco, CA, USA, pp.252-253, Feb. 2022. 10.1109\/isscc42614.2022.9731668","DOI":"10.1109\/ISSCC42614.2022.9731668"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] S.K. Esser, P.A. Merolla, J.V. Arthur, A.S. Cassidy, R. Appuswamy, A. Andreopoulos, D.J. Berg, J.L. McKinstry, T. Melano, D.R. Barch, C. di Nolfo, P. Datta, A. Amir, B. Taba, M.D. Flickner, and D.S. Modha, \u201cConvolutional networks for fast, energy-efficient neuromorphic computing,\u201d Proc. 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Kuroda, \u201cA 1.2nJ\/Classification 2.4mm<sup>2<\/sup> Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18\u03bcm CMOS,\u201d JSAP International Conference on Solid State Devices and Materials, Chiba, Japan, pp.750-751, 2022. 10.7567\/ssdm.2022.k-5-02","DOI":"10.7567\/SSDM.2022.K-5-02"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, \u201c1.2 nJ\/classification 2.4 mm<sup>2<\/sup> asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 \u00b5m CMOS,\u201d Japanese Journal of Applied Physics, vol.62, no.SC, p.SC1019, Jan. 2023. 10.35848\/1347-4065\/acac38","DOI":"10.35848\/1347-4065\/acac38"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] D. Bankman, L. Yang, B. Moons, M. Verhelst, and B. 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Park, S. Kwon, H.-S. Kim, T. Jeon, Y. Kang, H. Lee, D. Lee, J. Kim, Y.J. Lee, S. Park, J.-W. Jang, S.H. Ha, M.S. Kim, J. Bang, S.H. Lim, and I. Kang, \u201cA Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC,\u201d IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.246-248, Feb. 2022. 10.1109\/isscc42614.2022.9731639","DOI":"10.1109\/ISSCC42614.2022.9731639"},{"key":"33","doi-asserted-by":"crossref","unstructured":"[33] A. Kosuge, R. Sumikawa, Y.-C. Hsu, K. Shiba, M. Hamada, and T. Kuroda, \u201cA 183.4nJ\/inference 152.8\u03bcW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application,\u201d IEEE Symposium on VLSI Circuits, June 2023. 10.23919\/vlsitechnologyandcir57934.2023.10185297","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185297"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E107.C\/6\/E107.C_2023LHP0001\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T03:48:11Z","timestamp":1717213691000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E107.C\/6\/E107.C_2023LHP0001\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,1]]},"references-count":33,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2023lhp0001","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,6,1]]},"article-number":"2023LHP0001"}}