{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T10:03:55Z","timestamp":1648893835895},"reference-count":15,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2020,2,1]]},"DOI":"10.1587\/transfun.2019eal2133","type":"journal-article","created":{"date-parts":[[2020,1,31]],"date-time":"2020-01-31T22:09:40Z","timestamp":1580508580000},"page":"542-546","source":"Crossref","is-referenced-by-count":0,"title":["Sorting Matrix Architecture for Continuous Data Sequences"],"prefix":"10.1587","volume":"E103.A","author":[{"given":"Meiting","family":"XUE","sequence":"first","affiliation":[{"name":"Department of Instrument Engineering, Zhejiang University"}]},{"given":"Huan","family":"ZHANG","sequence":"additional","affiliation":[{"name":"College of Communication Engineering, Hangzhou Dianzi University"}]},{"given":"Weijun","family":"LI","sequence":"additional","affiliation":[{"name":"Department of Ningbo Institute of Technology, Zhejiang University"}]},{"given":"Feng","family":"YU","sequence":"additional","affiliation":[{"name":"Department of Instrument Engineering, Zhejiang University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] D. Koch and J. Torresen, \u201cFPGA Sort: A high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting,\u201d ACM FPGA&apos;11, pp.45-54, 2011. 10.1145\/1950413.1950427","DOI":"10.1145\/1950413.1950427"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] T. Usui, T.V. Chu, and K. Kise, \u201cA cost-effective and scalable merge sorter tree on FPGAs,\u201d IEEE Symp. Computing and Networking, pp.47-56, 2016. 10.1109\/candar.2016.0023","DOI":"10.1109\/CANDAR.2016.0023"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] S. Mashimo, T.V. Chu, and K. Kise, \u201cHigh-performance hardware merge sorter,\u201dIEEE Symp. FCCM, 2017. 10.1109\/fccm.2017.19","DOI":"10.1109\/FCCM.2017.19"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] S.H. Lin, P.Y. Chen, and Y.N. Lin, \u201cHardware design of low-power high-throughput sorting unit,\u201d IEEE Trans. Comput., vol.66, no.8, pp.1383-1395, Aug. 2017. 10.1109\/tc.2017.2672966","DOI":"10.1109\/TC.2017.2672966"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] R. Perez-Andrade, R. Cumplido, F.M.D. Campo, and C. Feregrino-Uribe, \u201cA versatile linear insertion sorter based on a FIFO scheme,\u201d IEEE Computer Society Annual Symposium on VLSI, pp.357-362, 2008. 10.1109\/isvlsi.2008.14","DOI":"10.1109\/ISVLSI.2008.14"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] A.A. Colavita, A. Cicuttin, F. Fratnik, and G. Capello, \u201cSORTCHIP: A VLSI implementation of a hardware algorithm for continuous data sorting,\u201d IEEE J. Solid-State Circuits, vol.38, no.6, pp.1076-1079, June 2003. 10.1109\/jssc.2003.811982","DOI":"10.1109\/JSSC.2003.811982"},{"key":"7","unstructured":"[7] C.S. Lin and B.D. Liu, \u201cDesign of a pipelined and expandable sorting architecture with simple control scheme,\u201d IEEE Symp. Circuits and Systems, pp.217-220, 2002. 10.1109\/iscas.2002.1010428"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] D.E. Carlson, J.T. Vogelstein, Q. Wu, W. Lian, M. Zhou, C.R. Stoetzner, D. Kipke, D. Weber, D.B. Dunson, and L. Carin, \u201cMultichannel electrophysiological spike sorting via joint dictionary learning and mixture modeling,\u201d IEEE Trans. Biomed. Eng., vol.61, no.1, pp.41-54, 2014. 10.1109\/tbme.2013.2275751","DOI":"10.1109\/TBME.2013.2275751"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] C. Chakrabarti and L.-Y. Wang, \u201cNovel sorting network-based architectures for rank order filters,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.2, no.4, pp.502-507, 1994. 10.1109\/92.335027","DOI":"10.1109\/92.335027"},{"key":"10","unstructured":"[10] C. Chakrabarti and L.-Y. Wang, \u201cNovel sorting network-based architectures for rank order filters,\u201d IEEE Trans. Knowl. Data Eng., pp.934-944, 1994."},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] G. Goetz, \u201cImplementing sorting in database systems,\u201d ACM Comput. Surv., vol.38, no.3, p.10, 2006. 10.1145\/1132960.1132964","DOI":"10.1145\/1132960.1132964"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] S. Dong, X. Wang, and X. Wang, \u201cA novel high-speed parallel scheme for data sorting algorithmbased on FPGa,\u201d IEEE Cong. Image and Signal Processing, pp.1-4, 2009. 10.1109\/cisp.2009.5302455","DOI":"10.1109\/CISP.2009.5302455"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] N. Matsumoto, K. Nakano, and Y. Ito, \u201cOptimal parallel hardware K-sorter and top K-sorter, with FPGA implementations,\u201d IEEE Symp. Parallel and Distributed Computing, pp.138-147, 2015. 10.1109\/ispdc.2015.23","DOI":"10.1109\/ISPDC.2015.23"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] T. Chen, W. Li, F. Yu, and Q. Xing, \u201cModular serial pipelined sorting architecture for continuous variable-length sequences with a very simple control strategy,\u201d IEICE Trans. Fundamentals, vol.E100-A, no.4, pp.1074-1078, April 2017. 10.1587\/transfun.e100.a.1074","DOI":"10.1587\/transfun.E100.A.1074"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] A. Farmahini-Farahani, H.J. Duwe, M.J. Schulte, and K. Compton, \u201cModular design of high-throughput, low-latency sorting units,\u201d IEEE Trans. Comput., vol.62, no.7, pp.1389-1402, 2013. 10.1109\/tc.2012.108","DOI":"10.1109\/TC.2012.108"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E103.A\/2\/E103.A_2019EAL2133\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T03:32:58Z","timestamp":1580527978000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E103.A\/2\/E103.A_2019EAL2133\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2,1]]},"references-count":15,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.2019eal2133","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"value":"0916-8508","type":"print"},{"value":"1745-1337","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,2,1]]}}}