{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,5,9]],"date-time":"2024-05-09T00:04:14Z","timestamp":1715213054562},"reference-count":18,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2021,11,1]]},"DOI":"10.1587\/transfun.2020kep0018","type":"journal-article","created":{"date-parts":[[2021,5,17]],"date-time":"2021-05-17T22:06:45Z","timestamp":1621289205000},"page":"1546-1554","source":"Crossref","is-referenced-by-count":1,"title":["A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits"],"prefix":"10.1587","volume":"E104.A","author":[{"given":"Ryosuke","family":"MATSUO","sequence":"first","affiliation":[{"name":"Graduate School of Informatics, Kyoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"SHIOMI","sequence":"additional","affiliation":[{"name":"Graduate School of Informatics, Kyoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tohru","family":"ISHIHARA","sequence":"additional","affiliation":[{"name":"Graduate School of Informatics, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hidetoshi","family":"ONODERA","sequence":"additional","affiliation":[{"name":"Graduate School of Informatics, Kyoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akihiko","family":"SHINYA","sequence":"additional","affiliation":[{"name":"NTT Nanophotonics Center"},{"name":"NTT Basic Research Laboratories"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masaya","family":"NOTOMI","sequence":"additional","affiliation":[{"name":"NTT Nanophotonics Center"},{"name":"NTT Basic Research Laboratories"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, \u201cA synthesis method for power-efficient integrated optical logic circuits towards light speed processing,\u201d 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.488-493, 2020. 10.1109\/isvlsi49217.2020.000-9","DOI":"10.1109\/ISVLSI49217.2020.000-9"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] A. Ceyhan, M. Jung, S. Panth, S.K. Lim, and A. Naeemi, \u201cImpact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts,\u201d Proc. IEEE Interconnect Technology Conference\/Advanced Metallization Conference, pp.345-348, May 2014. 10.1109\/iitc.2014.6831831","DOI":"10.1109\/IITC.2014.6831831"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] W. Zhao and Y. Cao, \u201cNew generation of predictive technology model for sub-45nm early design exploration,\u201d IEEE Trans. Electron Devices, vol.53, no.11, pp.2816-2823, Nov. 2006. 10.1109\/ted.2006.884077","DOI":"10.1109\/TED.2006.884077"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y. Vlasov, \u201cSilicon photonics for next generation computing systems,\u201d Proc. European Conference on Optical Communications, pp.1-2, Sept. 2008. 10.1109\/ecoc.2008.4729553","DOI":"10.1109\/ECOC.2008.4729553"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] N. Yamamoto, T. Ogawa, and K. Komori, \u201cPhotonic crystal directional coupler switch with small switching length and wide bandwidth,\u201d Opt. Express, vol.14, no.3, pp.1223-1229, Feb. 2006. 10.1364\/oe.14.001223","DOI":"10.1364\/OE.14.001223"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] J. Hardy and J. Shamir, \u201cOptics inspired logic architecture,\u201d Opt. Express, vol.15, no.1, pp.150-165, Jan. 2007. 10.1364\/oe.15.000150","DOI":"10.1364\/OE.15.000150"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] C. Condrat, P. Kalla, and S. Blair, \u201cLogic synthesis for integrated optics,\u201d Proc. Great lakes symposium on VLSI, pp.13-18, May 2011. 10.1145\/1973009.1973013","DOI":"10.1145\/1973009.1973013"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] R. Wille, O. Keszocze, C. Hopfmuller, and R. Drechsler, \u201cReverse BDD-based synthesis for splitter-free optical circuits,\u201d Proc. Asia-South Pacific Design Automation Conference, pp.172-177, Jan. 2015. 10.1109\/aspdac.2015.7059000","DOI":"10.1109\/ASPDAC.2015.7059000"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] Z. Zhao, Z. Wang, Z. Ying, S. Dhar, R.T. Chen, and D.Z. Pan, \u201cLogic synthesis for energy-efficient photonic integrated circuits,\u201d Proc. Asia-South Pacific Design Automation Conference, pp.355-360, Jan. 2018. 10.1109\/aspdac.2018.8297349","DOI":"10.1109\/ASPDAC.2018.8297349"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, \u201cBDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing,\u201d Proc. Asia-South Pacific Design Automation Conference, pp.355-360, Jan. 2019. 10.1145\/3287624.3287703","DOI":"10.1145\/3287624.3287703"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Z. Zhao, D. Liu, Z. Ying, B. Xu, C. Feng, R.T. Chen, and D.Z. Pan, \u201cExploiting wavelength division multiplexing for optical logic synthesis,\u201d 2019 Design, Automation Test in Europe Conference Exhibition (DATE), pp.1567-1570, March 2019. 10.23919\/date.2019.8715099","DOI":"10.23919\/DATE.2019.8715099"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Z. Zhao, J. Gu, Z. Ying, C. Feng, R.T. Chen, and D.Z. Pan, \u201cDesign technology for scalable and robust photonic integrated circuits: Invited paper,\u201d 2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp.1-7, Nov. 2019. 10.1109\/iccad45719.2019.8942045","DOI":"10.1109\/ICCAD45719.2019.8942045"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] H.C. Nguyen, N. Yazawa, S. Hashimoto, S. Otsuka, and T. Baba, \u201cSub-100\u00b5m photonic crystal Si optical modulators: Spectral, athermal, and high-speed performance,\u201d IEEE J. Sel. Topics Quantum Electron., vol.19, no.6, pp.127-137, June 2013. 10.1109\/jstqe.2013.2265193","DOI":"10.1109\/JSTQE.2013.2265193"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] K. Nozaki, S. Matsuo, T. Fujii, K. Takeda, A. Shinya, E. Kuramochi, and M. Notomi, \u201cFemtofarad optoelectronic integration demonstrating energy-saving signal conversion and nonlinear functions,\u201d Nature Photonics, vol.13, pp.454-459, July 2019. 10.1038\/s41566-019-0397-3","DOI":"10.1038\/s41566-019-0397-3"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] T. Egawa, T. Ishihara, H. Onodera, A. Shinya, S. Kita, K. Nozaki, K. Takata, and M. Notomi, \u201cMulti-level optimization for large fan-in optical logic circuits using integrated nanophotonics,\u201d IEEE International Conference on Rebooting Computing, pp.43-50, Nov. 2018. 10.1109\/icrc.2018.8638607","DOI":"10.1109\/ICRC.2018.8638607"},{"key":"16","unstructured":"[16] B.F. and F.H., \u201cA neural netlist of ten combinational benchmark circuits and translator in fortran,\u201d Int. Symp. Circuits and Systems (ISCAS), pp.663-698, June 1985."},{"key":"17","unstructured":"[17] Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, available online."},{"key":"18","unstructured":"[18] F. Somenzi, \u201cCUDD: CU decision diagram package,\u201d available online."}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E104.A\/11\/E104.A_2020KEP0018\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,8]],"date-time":"2024-05-08T04:40:51Z","timestamp":1715143251000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E104.A\/11\/E104.A_2020KEP0018\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,1]]},"references-count":18,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.2020kep0018","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"value":"0916-8508","type":"print"},{"value":"1745-1337","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,11,1]]},"article-number":"2020KEP0018"}}