{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T23:08:19Z","timestamp":1648940899676},"reference-count":32,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2022,3,1]]},"DOI":"10.1587\/transfun.2021vlp0002","type":"journal-article","created":{"date-parts":[[2021,8,30]],"date-time":"2021-08-30T22:09:29Z","timestamp":1630361369000},"page":"509-517","source":"Crossref","is-referenced-by-count":0,"title":["Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling"],"prefix":"10.1587","volume":"E105.A","author":[{"given":"Yutaka","family":"MASUDA","sequence":"first","affiliation":[{"name":"Graduate School of Informatics, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"NAGAYAMA","sequence":"additional","affiliation":[{"name":"Socionext Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"TaiYu","family":"CHENG","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, Osaka University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tohru","family":"ISHIHARA","sequence":"additional","affiliation":[{"name":"Graduate School of Informatics, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoichi","family":"MOMIYAMA","sequence":"additional","affiliation":[{"name":"Socionext Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masanori","family":"HASHIMOTO","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, Osaka University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. Han and M. Orshansky, \u201cApproximate computing: An emerging paradigm for energy-efficient design,\u201d Proc. ETS, pp.1-6, 2013. 10.1109\/ets.2013.6569370","DOI":"10.1109\/ETS.2013.6569370"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] V.K. Chippa, S.T. Chakradhar, K. Roy, and A. Raghunathan, \u201cAnalysis and characterization of inherent application resilience for approximate computing,\u201d Proc. DAC, pp.1-9, 2013. 10.1145\/2463209.2488873","DOI":"10.1145\/2463209.2488873"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] Q. Xu, T. Mytkowicz, and N.S. Kim, \u201cApproximate computing: A survey,\u201d IEEE Des. Test, vol.33, no.1, pp.8-22, 2016. 10.1109\/mdat.2015.2505723","DOI":"10.1109\/MDAT.2015.2505723"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] R. Hegde and N.R. Shanbhag, \u201cSoft digital signal processing,\u201d IEEE Trans. Very Large Scale Integr. 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ISLPED, pp.409-414, 2011. 10.1109\/islped.2011.5993675","DOI":"10.1109\/ISLPED.2011.5993675"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] P.K. Krause and I. Polian, \u201cAdaptive voltage over-scaling for resilient applications,\u201d Proc. DATE, pp.1-6, 2011. 10.1109\/date.2011.5763153","DOI":"10.1109\/DATE.2011.5763153"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] R. Ragavan, B. Barrois, C. Killian, and O. Sentieys, \u201cPushing the limits of voltage over-scaling for error-resilient applications,\u201d Proc. DATE, pp.476-481, 2017. 10.23919\/date.2017.7927036","DOI":"10.23919\/DATE.2017.7927036"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] R. Li, R. Naous, H. Fariborzi, and K.N. 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Mukhanov, and G. Karakonstantis, \u201cLow-power variation-aware cores based on dynamic data-dependent bitwidth truncation,\u201d Proc. DATE, pp.698-703, 2019. 10.23919\/date.2019.8714942","DOI":"10.23919\/DATE.2019.8714942"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, \u201cCritical path isolation and bit-width scaling are highly compatible for voltage over-scalable design,\u201d Proc. DATE, pp.1260-1265, 2021. 10.23919\/date51398.2021.9473946","DOI":"10.23919\/DATE51398.2021.9473946"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] S. Ghosh, S. Bhunia, and K. Roy, \u201cCRISTA: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation,\u201d Trans. Comput.-Aided Des. Integr. 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Gorlatch, \u201cSkelCL-A portable skeleton library for high-level GPU programming,\u201d IPDPS PhD Forum, pp.1176-1182, 2011. 10.1109\/ipdps.2011.269","DOI":"10.1109\/IPDPS.2011.269"},{"key":"23","unstructured":"[23] C. Chang and C. Lin, Fourclass, 1996. https:\/\/www.csie.ntu.edu.tw\/~cjlin\/libsvmtools\/datasets\/binary.html"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] T. Cheng, J. Yu, and M. Hashimoto, \u201cMinimizing power for neural network training with logarithm-approximate floating-point multiplier,\u201d Proc. PATMOS, pp.91-96, 2019. 10.1109\/patmos.2019.8862162","DOI":"10.1109\/PATMOS.2019.8862162"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] T.D. Burd, T.A. Pering, A.J. Stratakos, and R.W. Brodersen, \u201cA dynamic voltage scaled microprocessor system,\u201d IEEE J. Solid-State Circuits, vol.35, no.11, pp.1571-1580, 2000. 10.1109\/4.881202","DOI":"10.1109\/4.881202"},{"key":"26","doi-asserted-by":"publisher","unstructured":"[26] S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, \u201cA self-tuning DVS processor using delay-error detection and correction,\u201d IEEE J. Solid-State Circuits, vol.41, no.4, pp.792-804, 2006. 10.1109\/jssc.2006.870912","DOI":"10.1109\/JSSC.2006.870912"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] S. Hokimoto, T. Ishihara, and H. Onodera, \u201cMinimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing,\u201d Proc. SOCC, pp.1-6, 2016. 10.1109\/socc.2016.7905420","DOI":"10.1109\/SOCC.2016.7905420"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] N. Mehta and K.A.A. Makinwa, \u201cMinimum energy point tracking for sub-threshold digital CMOS circuits using an in-situ energy sensor,\u201d Proc. ISCAS, pp.570-573, 2013. 10.1109\/iscas.2013.6571906","DOI":"10.1109\/ISCAS.2013.6571906"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] K.A. Bowman, J.W. Tschanz, S.-L.L. Lu, P.A. Aseron, M.M. Khellah, A. Raychowdhury, B.M. Geuskens, C. Tokunaga, C.B. Wilkerson, T. Karnik, and V.K. De, \u201cA 45nm resilient microprocessor core for dynamic variation tolerance,\u201d IEEE J. Solid-State Circuits, vol.46, no.1, pp.194-208, 2011. 10.1109\/jssc.2010.2089657","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, \u201cAdaptive performance compensation with in-situ timing error predictive sensors for subthreshold circuits,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.20, no.2, pp.333-343, 2012. 10.1109\/tvlsi.2010.2101089","DOI":"10.1109\/TVLSI.2010.2101089"},{"key":"31","doi-asserted-by":"publisher","unstructured":"[31] S. Kim and M. Seok, \u201cVariation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique,\u201d IEEE J. Solid-State Circuits, vol.50, no.6, pp.1478-1490, 2015. 10.1109\/jssc.2015.2418713","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"32","doi-asserted-by":"publisher","unstructured":"[32] M. Cho, S.T. Kim, C. Tokunaga, C. Augustine, J.P. Kulkarni, K. Ravichandran, J.W. Tschanz, M.M. Khellah, and V. De, \u201cPostsilicon voltage guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating,\u201d IEEE J. Solid-State Circuits, vol.52, no.1, pp.50-63, 2017. 10.1109\/jssc.2016.2601319","DOI":"10.1109\/JSSC.2016.2601319"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E105.A\/3\/E105.A_2021VLP0002\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,5]],"date-time":"2022-03-05T03:21:55Z","timestamp":1646450515000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E105.A\/3\/E105.A_2021VLP0002\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,3,1]]},"references-count":32,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.2021vlp0002","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"value":"0916-8508","type":"print"},{"value":"1745-1337","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,3,1]]},"article-number":"2021VLP0002"}}