{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,19]],"date-time":"2025-11-19T11:37:03Z","timestamp":1763552223767,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2023,3,1]]},"DOI":"10.1587\/transfun.2022vlp0008","type":"journal-article","created":{"date-parts":[[2022,10,6]],"date-time":"2022-10-06T22:22:59Z","timestamp":1665094979000},"page":"560-574","source":"Crossref","is-referenced-by-count":5,"title":["An eFPGA Generation Suite with Customizable Architecture and IDE"],"prefix":"10.1587","volume":"E106.A","author":[{"given":"Morihiro","family":"KUGA","sequence":"first","affiliation":[{"name":"Faculty of Advanced Science and Thechnology, Kumamoto University"}]},{"given":"Qian","family":"ZHAO","sequence":"additional","affiliation":[{"name":"Kyushu Institute of Technology"}]},{"given":"Yuya","family":"NAKAZATO","sequence":"additional","affiliation":[{"name":"Dept. of Graduate School of Science and Thechnology, Kumamoto University"}]},{"given":"Motoki","family":"AMAGASAKI","sequence":"additional","affiliation":[{"name":"Faculty of Advanced Science and Thechnology, Kumamoto University"}]},{"given":"Masahiro","family":"IIDA","sequence":"additional","affiliation":[{"name":"Faculty of Advanced Science and Thechnology, Kumamoto University"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] Xilinx, Zynq-7000 SoC Overview, 2018. Retrieved Oct. 14, 2021 from https:\/\/www.xilinx.com\/content\/dam\/xilinx\/support\/documentation\/data_sheets\/ds190-Zynq-7000-Overview.pdf"},{"key":"2","unstructured":"[2] Achronix, Speedcore eFPGA Product Brief (PB028), 2020. Retrieved Oct. 14, 2021 from https:\/\/www.achronix.com\/sites\/default\/files\/docs\/Speedcore_eFPGA_Product_Brief_PB028.pdf"},{"key":"3","unstructured":"[3] QuickLogic, ArcticPro eFPGA, 2021. Retrieved Oct. 14, 2021 from https:\/\/www.quicklogic.com\/products\/efpga\/arcticpro-2\/"},{"key":"4","unstructured":"[4] FlexLogix, EFLX\u00ae eFPGA, 2021. Retrieved Oct. 14, 2021 from https:\/\/flex-logix.com\/efpga\/"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] P. Mohan, O. Atli, O. Kibar, M. Zackriya, L. Pileggi, and K. Mai, \u201cTop-down physical design of soft embedded FPGA fabrics,\u201d Proc. ACM\/SIGDA Int&apos;l Symp. on Field Programmable Gate Arrays (FPGA&apos;21), pp.1-10, 2021. https:\/\/doi.org\/10.1145\/3431920.3439297 10.1145\/3431920.3439297","DOI":"10.1145\/3431920.3439297"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] D. Koch, N. Dao, B. Healy, J. Yu, and A. Attwood, \u201cFABulous: An embedded FPGA framework,\u201d Proc. ACM\/SIGDA Int&apos;l Symp. on Field Programmable Gate Arrays (FPGA&apos;21), pp.45-56, 2021. https:\/\/doi.org\/10.1145\/3431920.3439302 10.1145\/3431920.3439302","DOI":"10.1145\/3431920.3439302"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] A. Li and D. Wentzlaff, \u201cPRGA: An open-source FPGA research and prototyping framework,\u201d Proc. ACM\/SIGDA Int&apos;l Symp. on Field Programmable Gate Arrays (FPGA&apos;21), pp.127-137, 2021. https:\/\/doi.org\/10.1145\/3431920.3439294 10.1145\/3431920.3439294","DOI":"10.1145\/3431920.3439294"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] X. Tang, E. Giacomin, B. Chauviere, A. Alacchi, and P-E. Gaillardon, \u201cOpenFPGA: An open-source framework for agile prototyping customizable FPGAs,\u201d Proc. IEEE Micro, vol.40, no.4, pp.41-48, July\/Aug. 2020. https:\/\/doi.org\/10.1109\/MM.2020.2995854 10.1109\/MM.2020.2995854","DOI":"10.1109\/MM.2020.2995854"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] J.H. Kim and J.H. Anderson, \u201cSynthesizable FPGA fabrics targetable by the verilog-to-routing (VTR) CAD flow,\u201d Proc. 25th Int&apos;l Conf. on Field Programmable Logic and Applications (FPL), pp.1-8, 2015. https:\/\/doi.org\/10.1109\/FPL.2015.7293955 10.1109\/FPL.2015.7293955","DOI":"10.1109\/FPL.2015.7293955"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] S.J.E. Wilton, C-H Ho, B. Quinton, P.H.W. Leong, and W. Luk, \u201cA synthesizable datapath-oriented embedded FPGA fabric for silicon debug applications,\u201d ACM Trans. Reconfigurable Technol. Syst., vol.1, no.1, Article 7, pp.1-25, March 2008. https:\/\/doi.org\/10.1145\/1331897.1331903 10.1145\/1331897.1331903","DOI":"10.1145\/1331897.1331903"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] N. Kafari, K. Bozman, and S.J.E. Wilton, \u201cArchitectures and algorithms for synthesizable embedded programmable logic cores,\u201d Proc. ACM\/SIGDA 11th Int&apos;l Symp. on Field programmable gate arrays (FPGA&apos;03), pp.3-11, 2003. https:\/\/doi.org\/10.1145\/611817.611820 10.1145\/611817.611820","DOI":"10.1145\/611817.611820"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] A. Yan and S.J.E. Wilton, \u201cSequential synthesizable embedded programmable logic cores for system-on-chip,\u201d Proc. IEEE 2004 Custom Integrated Circuits Conf. (IEEE Cat. no.04CH37571), pp.435-438, Orland, Oct. 2004. https:\/\/doi.org\/10.1109\/CICC.2004.1358844 10.1109\/CICC.2004.1358844","DOI":"10.1109\/CICC.2004.1358844"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] J. Rose, J. Luu, C.W. Yu, O. Densmore, J. Goeders, A. Somerville, K.B. Kent, P. Jamieson, and J. Anderson, \u201cThe VTR project: Architecture and CAD for FPGAs from verilog to routing,\u201d Proc. ACM\/SIGDA Int&apos;l Symp. on Field Programmable Gate Arrays (FPGA&apos;12), pp.77-86, 2012. https:\/\/doi.org\/10.1145\/2145694.2145708 10.1145\/2145694.2145708","DOI":"10.1145\/2145694.2145708"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Nakazato, M. Amagasaki, Q. Zhao, M. Iida, and M. Kuga, \u201cAutomation of domain-specific FPGA-IP generation and test,\u201d Proc. 11th Int&apos;l Symp. on Highly Efficient Accelerators and Reconfigurable Technologies (HEART&apos;21), Article 4, pp.1-6, 2021. https:\/\/doi.org\/10.1145\/3468044.3468048 10.1145\/3468044.3468048","DOI":"10.1145\/3468044.3468048"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] M. Amagasaki, R. Araki, M. Iida, and T. Sueyoshi, \u201cSLM: A scalable logic module architecture with less configuration memory,\u201d IEICE Trans. Fundamentals, vol.E99-A, no.12, pp.2500-2506, Dec. 2016. http:\/\/dx.doi.org\/10.1587\/transfun.E99.A.2500 10.1587\/transfun.E99.A.2500","DOI":"10.1587\/transfun.E99.A.2500"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] M. Amagasaki, Y. Nishitani, K. Inoue, M. Iida, M. Kuga, and T. Sueyoshi, \u201cPhysical fault detection and recovery methods for system-LSI loaded FPGA-IP core,\u201d IEICE Trans. Inf. &amp; Syst., vol.E100-D, no.4, pp.633-644, April 2017. https:\/\/doi.org\/10.1587\/transinf.2016AWI0005 10.1587\/transinf.2016AWI0005","DOI":"10.1587\/transinf.2016AWI0005"},{"key":"17","unstructured":"[17] C. Wolf, Yosys Open SYnthesis Suite, Retrieved Oct. 14, 2021 from http:\/\/www.clifford.at\/yosys\/"},{"key":"18","unstructured":"[18] Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Retrieved Oct. 14, 2021 from http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/"},{"key":"19","unstructured":"[19] Xilinx, Vivado\u00ae ML, Retrieved Oct. 14, 2021 from https:\/\/www.xilinx.com\/products\/design-tools\/vivado.html"},{"key":"20","unstructured":"[20] Intel, Quartus\u00ae Prime, Retrieved Oct. 14, 2021 from https:\/\/www.intel.com\/content\/www\/us\/en\/software\/programmable\/quartus-prime\/overview.html"},{"key":"21","unstructured":"[21] S. Obilisetty, \u201cChip design and cloud: The good, the emerging, and the potential,\u201d Design Automation Conf. (DAC&apos;21), Session 58, Dec. 2021."},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] Q. Zhao, K. Inoue, M. Amagasaki, M. Iida, M. Kuga, and T. Sueyoshi, \u201cFPGA design framework combined with commercial VLSI CAD,\u201d IEICE Trans. Inf. &amp; Syst., vol.E96-D, no.8, pp.1602-1612, Aug. 2013. https:\/\/doi.org\/10.1587\/transinf.E96.D.1602 10.1587\/transinf.E96.D.1602","DOI":"10.1587\/transinf.E96.D.1602"},{"key":"23","unstructured":"[23] OpenSTA, Retrieved Oct. 14, 2021 from http:\/\/opensta.org\/"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] J.H. Anderson and Q. Wang, \u201cArea-efficient FPGA logic elements: Architecture and synthesis,\u201d Proc. 16th Asia and South Pacific Design Automation Conf. (ASP-DAC&apos;11), pp.369-375, 2011. https:\/\/doi.org\/10.1109\/ASPDAC.2011.5722215 10.1109\/ASPDAC.2011.5722215","DOI":"10.1109\/ASPDAC.2011.5722215"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] Z. Zilic and Z.G. Vranesic, \u201cUsing decision diagrams to design ULMs for FPGAs,\u201d IEEE Trans. Comput., vol.47, no.9, pp.971-982, Sept. 1998. https:\/\/doi.org\/10.1109\/12.713316 10.1109\/12.713316","DOI":"10.1109\/12.713316"},{"key":"26","doi-asserted-by":"publisher","unstructured":"[26] M. Iida, M. Amagasaki, Y. Okamoto, Q. Zhao, and T. Sueyoshi, \u201cCOGRE: A configuration memory reduced reconfigurable logic cell architecture for area minimization,\u201d IEICE Trans. Inf. &amp; Syst., vol.E95-D, no.2, pp.294-302, Feb. 2012. https:\/\/doi.org\/10.1587\/transinf.E95.D.294 10.1587\/transinf.E95.D.294","DOI":"10.1587\/transinf.E95.D.294"},{"key":"27","unstructured":"[27] K.S. McElvain, IWLS&apos;93 Benchmark Set: Version 4.0, Distributed as part of the MCNC Int&apos;l Workshop on Logic Synthesis &apos;93 benchmark distribution, 1993."},{"key":"28","unstructured":"[28] V. Betz, 175.vpr SPEC CPU2000 Benchmark Description File, Retrieved Oct. 14, 2021. from http:\/\/www.spec.org\/osg\/cpu2000\/CINT2000\/175.vpr\/docs\/175.vpr.html"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] D. Chai and A. Kuehlmann, \u201cBuilding a better Boolean matcher and symmetry detector,\u201d Proc. Conf. Design, automation and test in Europe (DATE&apos;06), pp.1079-1084, 2006. https:\/\/doi.org\/10.1109\/DATE.2006.243959 10.1109\/DATE.2006.243959","DOI":"10.1109\/DATE.2006.243959"},{"key":"30","doi-asserted-by":"publisher","unstructured":"[30] E. Ahmed and J. Rose, \u201cThe effect of LUT and cluster size on deep-submicron FPGA performance and density,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.12, no.3, pp.288-298, March 2004. https:\/\/doi.org\/10.1109\/TVLSI.2004.824300 10.1109\/TVLSI.2004.824300","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] G.G. Lemieux and D.M. Lewis, \u201cAnalytical framework for switch block design,\u201d Proc. 12th Int&apos;l Conf. on Field-Programmable Logic and Applications (FPL&apos;02), pp.122-131, 2002. https:\/\/doi.org\/10.1007\/3-540-46117-5_14 10.1007\/3-540-46117-5_14","DOI":"10.1007\/3-540-46117-5_14"},{"key":"32","doi-asserted-by":"publisher","unstructured":"[32] K. Inoue, M. Koga, M.i Amagasaki, M. Iida, Y. Ichida, M. Saji, J. Iida, and T. Sueyoshi, \u201cAn easily testable routing architecture and prototype chip,\u201d IEICE Trans. Inf. &amp; Syst., vol.E95-D, no.2, pp.303-313, Feb. 2012. https:\/\/doi.org\/10.1587\/transinf.E95.D.303 10.1587\/transinf.E95.D.303","DOI":"10.1587\/transinf.E95.D.303"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E106.A\/3\/E106.A_2022VLP0008\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,3,4]],"date-time":"2023-03-04T03:21:47Z","timestamp":1677900107000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E106.A\/3\/E106.A_2022VLP0008\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3,1]]},"references-count":32,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2023]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.2022vlp0008","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"type":"print","value":"0916-8508"},{"type":"electronic","value":"1745-1337"}],"subject":[],"published":{"date-parts":[[2023,3,1]]},"article-number":"2022VLP0008"}}