{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,5]],"date-time":"2024-10-05T03:40:08Z","timestamp":1728099608763},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2024,10,1]]},"DOI":"10.1587\/transfun.2023eap1135","type":"journal-article","created":{"date-parts":[[2024,5,27]],"date-time":"2024-05-27T22:16:36Z","timestamp":1716848196000},"page":"1582-1594","source":"Crossref","is-referenced-by-count":0,"title":["High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA"],"prefix":"10.1587","volume":"E107.A","author":[{"given":"Meiting","family":"XUE","sequence":"first","affiliation":[{"name":"Department of Cyberspace, Hangzhou Dianzi University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenqi","family":"WU","sequence":"additional","affiliation":[{"name":"College of Biomedical Engineering and Instrument Science, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinfeng","family":"LUO","sequence":"additional","affiliation":[{"name":"College of Biomedical Engineering and Instrument Science, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yixuan","family":"ZHANG","sequence":"additional","affiliation":[{"name":"School of Cyber Security, University of Chinese Academy of Sciences"},{"name":"School of Computer Science and Technology, Hangzhou Dianzi University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bei","family":"ZHAO","sequence":"additional","affiliation":[{"name":"College of Biomedical Engineering and Instrument Science, Zhejiang University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] P. Papaphilippou and W. Luk, \u201cAccelerating database systems using fpgas: A survey,\u201d 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp.125-1255, IEEE, 2018. 10.1109\/fpl.2018.00030","DOI":"10.1109\/FPL.2018.00030"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] A. Putnam, A.M. Caulfield, E.S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G.P. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P.Y. Xiao, and D. Burger, \u201cA reconfigurable fabric for accelerating large-scale datacenter services,\u201d 2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA), pp.13-24, IEEE, 2014. 10.1109\/ISCA.2014.6853195","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] I. Koumarelas, A. Naskos, and A. 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Zhang, \u201cRelational query processing on opencl-based FPGAs,\u201d 2016 26th International Conference on Field Programmable Logic and Applications (FPL), pp.1-10, IEEE, 2016. 10.1109\/fpl.2016.7577329","DOI":"10.1109\/FPL.2016.7577329"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] D. Li, L. Huang, T. Gao, Y. Feng, A. Tavares, and K. Wang, \u201cAn extended nonstrict partially ordered set-based configurable linear sorter on FPGAs,\u201d IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.39, no.5, pp.1031-1044, 2020. 10.1109\/tcad.2020.2977074","DOI":"10.1109\/TCAD.2020.2977074"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] D. Li, R. Du, Z. Liu, T. Yang, and B. Cui, \u201cMulti-copy cuckoo hashing,\u201d 2019 IEEE 35th International Conference on Data Engineering (ICDE), pp.1226-1237, IEEE, 2019. 10.1109\/icde.2019.00112","DOI":"10.1109\/ICDE.2019.00112"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] J. Zhan, W. Jiang, Y. Li, J. Wu, J. Zhu, and J. Yu, \u201cAccelerating queries of big data systems by storage-side CPU-FPGA co-design,\u201d IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.41, no.7, pp.2128-2141, 2022. 10.1109\/tcad.2021.3100743","DOI":"10.1109\/TCAD.2021.3100743"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] \u00c7. Balkesen, J. Teubner, G. Alonso, and M.T. \u00d6zsu, \u201cMain-memory hash joins on modern processor architectures,\u201d IEEE Trans. Knowl. Data Eng., vol.27, no.7, pp.1754-1766, 2014. 10.1109\/TKDE.2014.2313874","DOI":"10.1109\/TKDE.2014.2313874"},{"key":"17","unstructured":"[17] K. Huang, \u201cMulti-way hash join based on FPGAs,\u201d 2018."},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] C. Balkesen, G. Alonso, J. Teubner, and M.T. \u00d6zsu, \u201cMulti-core, main-memory joins: Sort vs. hash revisited,\u201d Proc. VLDB Endowment, vol.7, no.1, pp.85-96, 2013. 10.14778\/2732219.2732227","DOI":"10.14778\/2732219.2732227"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] J. Paul, B. He, S. Lu, and C.T. Lau, \u201cRevisiting hash join on graphics processors: A decade later,\u201d Distrib. Parallel Databases, vol.38, no.4, pp.771-793, 2020. 10.1007\/s10619-019-07280-z","DOI":"10.1007\/s10619-019-07280-z"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] R. Chen and V.K. Prasanna, \u201cAccelerating equi-join on a CPU-FPGA heterogeneous platform,\u201d 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.212-219, IEEE, 2016. 10.1109\/fccm.2016.62","DOI":"10.1109\/FCCM.2016.62"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] P. Papaphilippou, H. Pirk, and W. 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Pionteck, \u201cHardware-accelerated join processing in large semantic web databases with FPGAs,\u201d in 2013 International Conference on High Performance Computing & Simulation (HPCS), pp.131-138, IEEE, 2013. 10.1109\/hpcsim.2013.6641403","DOI":"10.1109\/HPCSim.2013.6641403"},{"key":"33","doi-asserted-by":"publisher","unstructured":"[33] W. Chen, W. Li, and F. Yu, \u201cModular pipeline architecture for accelerating join operation in RDBMS,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.67, no.11, pp.2662-2666, 2020. 10.1109\/tcsii.2020.2968499","DOI":"10.1109\/TCSII.2020.2968499"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E107.A\/10\/E107.A_2023EAP1135\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,5]],"date-time":"2024-10-05T03:26:53Z","timestamp":1728098813000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E107.A\/10\/E107.A_2023EAP1135\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,1]]},"references-count":33,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.2023eap1135","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"type":"print","value":"0916-8508"},{"type":"electronic","value":"1745-1337"}],"subject":[],"published":{"date-parts":[[2024,10,1]]},"article-number":"2023EAP1135"}}