{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,3,3]],"date-time":"2024-03-03T00:05:00Z","timestamp":1709424300235},"reference-count":22,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2024,3,1]]},"DOI":"10.1587\/transfun.2023vlp0008","type":"journal-article","created":{"date-parts":[[2023,8,30]],"date-time":"2023-08-30T22:24:52Z","timestamp":1693434292000},"page":"540-548","source":"Crossref","is-referenced-by-count":0,"title":["Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits"],"prefix":"10.1587","volume":"E107.A","author":[{"given":"Jiaxuan","family":"LU","sequence":"first","affiliation":[{"name":"Graduate School of Informatics, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yutaka","family":"MASUDA","sequence":"additional","affiliation":[{"name":"Graduate School of Informatics, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tohru","family":"ISHIHARA","sequence":"additional","affiliation":[{"name":"Graduate School of Informatics, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. 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Topics Comput., vol.5, no.2, pp.164-178, 2017. 10.1109\/tetc.2017.2673548","DOI":"10.1109\/TETC.2017.2673548"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E107.A\/3\/E107.A_2023VLP0008\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T03:30:13Z","timestamp":1709350213000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E107.A\/3\/E107.A_2023VLP0008\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3,1]]},"references-count":22,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.2023vlp0008","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"value":"0916-8508","type":"print"},{"value":"1745-1337","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,3,1]]},"article-number":"2023VLP0008"}}