{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T06:12:19Z","timestamp":1740809539888,"version":"3.38.0"},"reference-count":25,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2025,3,1]]},"DOI":"10.1587\/transfun.2024cip0009","type":"journal-article","created":{"date-parts":[[2024,10,17]],"date-time":"2024-10-17T22:12:09Z","timestamp":1729203129000},"page":"215-226","source":"Crossref","is-referenced-by-count":0,"title":["Multi-Bit DDLA: Non-Profiled Deep Learning Side-Channel Attacks Using Multi-Bit Label against Hardware-Implemented AES"],"prefix":"10.1587","volume":"E108.A","author":[{"given":"Yuta","family":"FUKUDA","sequence":"first","affiliation":[{"name":"Graduate School of Science and Technology, Ritsumeikan University"}]},{"given":"Kota","family":"YOSHIDA","sequence":"additional","affiliation":[{"name":"Department of Science and Engineering, Ritsumeikan University"}]},{"given":"Takeshi","family":"FUJINO","sequence":"additional","affiliation":[{"name":"Department of Science and Engineering, Ritsumeikan University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] S. Chari, J.R. Rao, and P. Rohatgi, \u201cTemplate attacks,\u201d International Workshop on Cryptographic Hardware and Embedded Systems, pp.13-28, Springer, 2002. 10.1007\/3-540-36400-5_3","DOI":"10.1007\/3-540-36400-5_3"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] P. Kocher, J. Jaffe, and B. Jun, \u201cDifferential power analysis,\u201d Annual International Cryptology Conference, pp.388-397, Springer, 1999. 10.1007\/3-540-48405-1_25","DOI":"10.1007\/3-540-48405-1_25"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] E. Brier, C. Clavier, and F. Olivier, \u201cCorrelation power analysis with a leakage model,\u201d Cryptographic Hardware and Embedded Systems - CHES 2004, M. Joye and J.J. Quisquater, eds., Berlin, Heidelberg, pp.16-29, Springer Berlin Heidelberg, 2004. 10.1007\/978-3-540-28632-5_2","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] B. Gierlichs, L. Batina, P. Tuyls, and B. Preneel, \u201cMutual information analysis,\u201d Cryptographic Hardware and Embedded Systems - CHES 2008, E. Oswald and P. Rohatgi, eds., Berlin, Heidelberg, pp.426-442, Springer Berlin Heidelberg, 2008. 10.1007\/978-3-540-85053-3_27","DOI":"10.1007\/978-3-540-85053-3_27"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] H. Maghrebi, T. Portigliatti, and E. Prouff, \u201cBreaking cryptographic implementations using deep learning techniques,\u201d International Conference on Security, Privacy, and Applied Cryptography Engineering, pp.3-26, Springer, 2016. 10.1007\/978-3-319-49445-6_1","DOI":"10.1007\/978-3-319-49445-6_1"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] E. Cagli, C. Dumas, and E. Prouff, \u201cConvolutional neural networks with data augmentation against jitter-based countermeasures\u2006\u2014\u2006Profiling attacks without pre-processing,\u201d Cryptographic Hardware and Embedded Systems - CHES 2017 - 19th International Conference, Taipei, Taiwan, Sept. 2017, Proceedings, W. Fischer and N. Homma, eds., Lecture Notes in Computer Science, vol.10529, pp.45-68, Springer, 2017. 10.1007\/978-3-319-66787-4_3","DOI":"10.1007\/978-3-319-66787-4_3"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] B. Hettwer, T. Horn, S. Gehrer, and T. G\u00fcneysu, \u201cEncoding power traces as images for efficient side-channel analysis,\u201d 2020 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2020, San Jose, CA, USA, Dec. 2020, pp.46-56, IEEE, 2020. 10.1109\/host45689.2020.9300289","DOI":"10.1109\/HOST45689.2020.9300289"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] T. Kubota, K. Yoshida, M. Shiozaki, and T. Fujino, \u201cDeep learning side-channel attack against hardware implementations of AES,\u201d 2019 22nd Euromicro Conference on Digital System Design (DSD), pp.261-268, 2019. 10.1109\/dsd.2019.00046","DOI":"10.1109\/DSD.2019.00046"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] B. Timon, \u201cNon-profiled deep learning-based side-channel attacks with sensitivity analysis,\u201d IACR Transactions on Cryptographic Hardware and Embedded Systems, vol.2019, no.2, pp.107-131, Feb. 2019. 10.46586\/tches.v2019.i2.107-131","DOI":"10.46586\/tches.v2019.i2.107-131"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] S. Picek, A. Heuser, A. Jovic, S. Bhasin, and F. Regazzoni, \u201cThe curse of class imbalance and conflicting metrics with machine learning for side-channel evaluations,\u201d IACR Trans. Cryptogr. Hardw. Embed. Syst., vol.2019, no.1, pp.209-237, 2019. 10.46586\/tches.v2019.i1.209-237","DOI":"10.46586\/tches.v2019.i1.209-237"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] L. Zhang, X. Xing, J. Fan, Z. Wang, and S. Wang, \u201cMultilabel deep learning-based side-channel attack,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.40, no.6, pp.1207-1216, 2021. 10.1109\/tcad.2020.3033495","DOI":"10.1109\/TCAD.2020.3033495"},{"key":"12","unstructured":"[12] E. Prouff, R. Strullu, R. Benadjila, E. Cagli, and C. Dumas, \u201cStudy of deep learning techniques for side-channel analysis and introduction to ASCAD database,\u201d IACR Cryptol. ePrint Arch., p.53, 2018."},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] K. Kuroda, Y. Fukuda, K. Yoshida, and T. Fujino, \u201cPractical aspects on non-profiled deep-learning side-channel attacks against AES software implementation with two types of masking countermeasures including RSM,\u201d Proc. 5th Workshop on Attacks and Solutions in Hardware Security, ASHES\u201921, New York, NY, USA, p.29-40, Association for Computing Machinery, 2021. 10.1145\/3474376.3487285","DOI":"10.1145\/3474376.3487285"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] M. Nassar, Y. Souissi, S. Guilley, and J. Danger, \u201cRSM: A small and fast countermeasure for aes, secure against 1st and 2nd-order zero-offset scas,\u201d 2012 Design, Automation Test in Europe Conference Exhibition (DATE), pp.1173-1178, 2012. 10.1109\/date.2012.6176671","DOI":"10.1109\/DATE.2012.6176671"},{"key":"15","unstructured":"[15] K. Tiri and I. Verbauwhede, \u201cA logic level design methodology for a secure DPA resistant ASIC or FPGA implementation,\u201d 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Feb. 2004, Paris, France, pp.246-251, IEEE Computer Society, 2004. 10.1109\/date.2004.1268856"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] Y. Fukuda, K. Yoshida, H. Hashimoto, and T. Fujino, \u201cDeep learning side-channel attacks against lightweight sca countermeasure RSM-AES,\u201d 2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp.1-6, 2021. 10.1109\/asianhost53231.2021.9699488","DOI":"10.1109\/AsianHOST53231.2021.9699488"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] D. Suzuki, M. Saeki, K. Shimizu, and T. Matsumoto, \u201cHow to decide selection functions for power analysis: From the viewpoint of hardware architecture of block ciphers,\u201d IEICE Trans. Fundamentals, vol.E94-A, no.1, pp.200-210, Jan. 2011. 10.1587\/transfun.e94.a.200","DOI":"10.1587\/transfun.E94.A.200"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] R. Bevan and E. Knudsen, \u201cWays to enhance differential power analysis,\u201d Proc. 5th International Conference on Information Security and Cryptology, ICISC\u201902, Berlin, Heidelberg, p.327-342, Springer-Verlag, 2002. 10.1007\/3-540-36552-4_23","DOI":"10.1007\/3-540-36552-4_23"},{"key":"19","unstructured":"[19] T.S. Messerges, E.A. Dabbish, and R.H. Sloan, \u201cInvestigations of power analysis attacks on smartcards,\u201d Smartcard, vol.99, pp.151-161, 1999."},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] A. Moradi, S. Guilley, and A. Heuser, \u201cDetecting hidden leakages,\u201d Applied Cryptography and Network Security, I. Boureanu, P. Owesarski, and S. Vaudenay, eds., Cham, pp.324-342, Springer International Publishing, 2014. 10.1007\/978-3-319-07536-5_20","DOI":"10.1007\/978-3-319-07536-5_20"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] Y. Fukuda, K. Yoshida, H. Hashimoto, K. Kuroda, and T. Fujino, \u201cProfiling deep learning side-channel attacks using multi-label against AES circuits with RSM countermeasure,\u201d IEICE Trans. Fundamentals, vol.E106-A, no.3, pp.294-305, March 2023. 10.1587\/transfun.2022cip0015","DOI":"10.1587\/transfun.2022CIP0015"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] Y. Fukuda, K. Yoshida, K. Kuroda, and T. Fujino, \u201cWaveform data augmentation using conditional VAE for deep learning side-channel attacks against AES circuit,\u201d Journal of Signal Processing, vol.26, no.4, pp.99-102, 2022. 10.2299\/jsp.26.99","DOI":"10.2299\/jsp.26.99"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] J. Kim, S. Picek, A. Heuser, S. Bhasin, and A. Hanjalic, \u201cMake some noise. Unleashing the power of convolutional neural networks for profiled side-channel analysis,\u201d IACR Trans. Cryptogr. Hardw. Embed. Syst., vol.2019, no.3, pp.148-179, 2019. 10.46586\/tches.v2019.i3.148-179","DOI":"10.46586\/tches.v2019.i3.148-179"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] N.T. Do, P.C. Le, V.P. Hoang, V.S. Doan, H.G. Nguyen, and C.K. Pham, \u201cMO-DLSCA: Deep learning based non-profiled side channel analysis using multi-output neural networks,\u201d 2022 International Conference on Advanced Technologies for Communications (ATC), pp.245-250, 2022. 10.1109\/atc55345.2022.9943024","DOI":"10.1109\/ATC55345.2022.9943024"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] Q. Wang, Y. Ma, K. Zhao, and Y. Tian, \u201cA comprehensive survey of loss functions in machine learning,\u201d Annal. Data Sci., vol.9, no.2, pp.187-212, April 2022. 10.1007\/s40745-020-00253-5","DOI":"10.1007\/s40745-020-00253-5"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E108.A\/3\/E108.A_2024CIP0009\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T03:30:12Z","timestamp":1740799812000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E108.A\/3\/E108.A_2024CIP0009\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,1]]},"references-count":25,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.2024cip0009","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"type":"print","value":"0916-8508"},{"type":"electronic","value":"1745-1337"}],"subject":[],"published":{"date-parts":[[2025,3,1]]},"article-number":"2024CIP0009"}}