{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T06:12:21Z","timestamp":1740809541318,"version":"3.38.0"},"reference-count":19,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2025,3,1]]},"DOI":"10.1587\/transfun.2024tap0007","type":"journal-article","created":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T22:11:33Z","timestamp":1725833493000},"page":"376-383","source":"Crossref","is-referenced-by-count":0,"title":["Double-Stack Erasure-Filled Channel and Level-By-Level Error Correction"],"prefix":"10.1587","volume":"E108.A","author":[{"given":"Hironori","family":"UCHIKAWA","sequence":"first","affiliation":[{"name":"Memory Division, Kioxia Corporation"}]},{"given":"Manabu","family":"HAGIWARA","sequence":"additional","affiliation":[{"name":"Department of Mathematics and Informatics, Chiba University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] G. Mappouras, A. Vahid, R. Calderbank, and D.J. Sorin, \u201cGreenFlag: Protecting 3D-racetrack memory from shift errors,\u201d 2019 49th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN), pp.1-12, IEEE, 2019. 10.1109\/dsn.2019.00016","DOI":"10.1109\/DSN.2019.00016"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] Y.M. Chee, H.M. Kiah, A. Vardy, V.K. Vu, and E. Yaakobi, \u201cCoding for racetrack memories,\u201d IEEE Trans. Inf. Theory, vol.64, no.11, pp.7094-7112, 2018. 10.1109\/TIT.2018.2807480","DOI":"10.1109\/TIT.2018.2807480"},{"key":"3","unstructured":"[3] A. Vahid, G. Mappouras, D.J. Sorin, and R. Calderbank, \u201cCorrecting two deletions and insertions in racetrack memory,\u201d arXiv preprint arXiv:1701.06478, 2017. 10.48550\/arXiv.1701.06478"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] M. Cheraghchi and J. Ribeiro, \u201cAn overview of capacity results for synchronization channels,\u201d IEEE Trans. Inf. Theory, vol.67, no.6, pp.3207-3232, June 2021. 10.1109\/tit.2020.2997329","DOI":"10.1109\/TIT.2020.2997329"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Li, X. Lin, P. Li, S. Zhao, Z. Si, G. Wei, B. Koopmans, R. Lavrijsen, and W. Zhao, \u201cUltralow power and shifting-discretized magnetic racetrack memory device driven by chirality switching and spin current,\u201d arXiv preprint arXiv:2305.04671, May 2023. 10.48550\/arXiv.2305.04671","DOI":"10.1021\/acsami.3c06447"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] A.J. Annunziata, M.C. Gaidis, L. Thomas, C.W. Chien, C.C. Hung, P. Chevalier, E.J. O\u2019Sullivan, J.P. Hummel, E.A. Joseph, Y. Zhu, T. Topuria, E. Delenia, P.M. Rice, S.S.P. Parkin, and W.J. Gallagher, \u201cRacetrack memory cell array with integrated magnetic tunnel junction readout,\u201d 2011 International Electron Devices Meeting, pp.24.3.1-24.3.4, Dec. 2011. 10.1109\/iedm.2011.6131604","DOI":"10.1109\/IEDM.2011.6131604"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] S. Ghosh, A. Iyengar, S. Motaman, R. Govindaraj, J.W. Jang, J. Chung, J. Park, X. Li, R. Joshi, and D. Somasekhar, \u201cOverview of circuits, systems, and applications of spintronics,\u201d IEEE Trans. Emerg. Sel. Topics Circuits Syst., vol.6, no.3, pp.265-278, Sept. 2016. 10.1109\/jetcas.2016.2601310","DOI":"10.1109\/JETCAS.2016.2601310"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] S. Ollivier, S. Longofono, P. Dutta, J. Hu, S. Bhanja, and A.K. Jones, \u201cToward comprehensive shifting fault tolerance for Domain-Wall memories with PIETT,\u201d IEEE Trans. Comput., vol.72, no.4, pp.1095-1109, 2023. 10.1109\/tc.2022.3188206","DOI":"10.1109\/TC.2022.3188206"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] M. Hagiwara, \u201cMulti deletion\/substitution\/erasure error-correcting codes for information in array design,\u201d IEICE Trans. Fundamentals, vol.E106-A, no.3, pp.368-374, March 2023. 10.1587\/transfun.2022tap0008","DOI":"10.1587\/transfun.2022TAP0008"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] L. Welter, R. Bitar, A. Wachter-Zeh, and E. Yaakobi, \u201cMultiple criss-cross insertion and deletion correcting codes,\u201d IEEE Trans. Inf. Theory, vol.68, no.6, pp.3767-3779, June 2022. 10.1109\/tit.2022.3152398","DOI":"10.1109\/TIT.2022.3152398"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Y.M. Chee, M. Hagiwara, and V. Van Khu, \u201cTwo dimensional deletion correcting codes and their applications,\u201d 2021 IEEE International Symposium on Information Theory (ISIT), pp.2792-2797, IEEE, July 2021. 10.1109\/isit45174.2021.9517903","DOI":"10.1109\/ISIT45174.2021.9517903"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] R. Shibata and H. Yashima, \u201cSymbol-level detection with matched non-binary LDPC codes for position errors in racetrack memories,\u201d IEEE Trans. Magn., vol.59, no.2, pp.1-9, Feb. 2023. 10.1109\/tmag.2022.3214932","DOI":"10.1109\/TMAG.2022.3214932"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] H. Koremura and H. Kaneko, \u201cInsertion\/deletion\/substitution error correction by a modified successive cancellation decoding of polar code,\u201d IEICE Trans. Fundamentals, vol.E103-A, no.4, pp.695-703, April 2020. 10.1587\/transfun.2019eap1079","DOI":"10.1587\/transfun.2019EAP1079"},{"key":"14","doi-asserted-by":"publisher","unstructured":"[14] R. Goto and K. Kasai, \u201cSparse graph codes for channels with synchronous errors,\u201d IEICE Trans. Fundamentals, vol.E101-A, no.12, pp.2064-2071, Dec. 2018. 10.1587\/transfun.e101.a.2064","DOI":"10.1587\/transfun.E101.A.2064"},{"key":"15","unstructured":"[15] V.I. Levenshtein, \u201cBinary codes capable of correcting deletions, insertions, and reversals,\u201d Soviet Physics Dokl., vol.10, no.8, pp.707-710, 1966."},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] W. Anacker, G.F. Bland, P. Pleshko, and P.E. Stuckert, \u201cOn the design and performance of a small 60-nsec destructive readout magnetic film memory,\u201d IBM J. Res. Dev., vol.10, no.1, pp.41-50, Jan. 1966. 10.1147\/rd.101.0041","DOI":"10.1147\/rd.101.0041"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] R. Gallager, \u201cLow-density parity-check codes,\u201d IRE Trans. Inf. Theory, vol.8, no.1, pp.21-28, 1962. 10.1109\/tit.1962.1057683","DOI":"10.1109\/TIT.1962.1057683"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] M.P.C. Fossorier, \u201cQuasi-cyclic low-density parity-check codes from circulant permutation matrices,\u201d IEEE Trans. Inf. Theory, vol.50, no.8, pp.1788-1793, 2004. 10.1109\/tit.2004.831841","DOI":"10.1109\/TIT.2004.831841"},{"key":"19","unstructured":"[19] X.Y. Hu, E. Eleftheriou, and D.M. Arnold, \u201cProgressive edge-growth Tanner graphs,\u201d GLOBECOM\u201901: IEEE Global Telecommunications Conference, pp.995-1001, IEEE, 2001. 10.1109\/glocom.2001.965567"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E108.A\/3\/E108.A_2024TAP0007\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T03:30:49Z","timestamp":1740799849000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E108.A\/3\/E108.A_2024TAP0007\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,1]]},"references-count":19,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.2024tap0007","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"type":"print","value":"0916-8508"},{"type":"electronic","value":"1745-1337"}],"subject":[],"published":{"date-parts":[[2025,3,1]]},"article-number":"2024TAP0007"}}