{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T09:24:51Z","timestamp":1775467491160,"version":"3.50.1"},"reference-count":14,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/transfun.e99.a.2500","type":"journal-article","created":{"date-parts":[[2016,11,30]],"date-time":"2016-11-30T17:10:06Z","timestamp":1480525806000},"page":"2500-2506","source":"Crossref","is-referenced-by-count":10,"title":["SLM: A Scalable Logic Module Architecture with Less Configuration Memory"],"prefix":"10.1587","volume":"E99.A","author":[{"given":"Motoki","family":"AMAGASAKI","sequence":"first","affiliation":[{"name":"Graduate School of Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryo","family":"ARAKI","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiro","family":"IIDA","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshinori","family":"SUEYOSHI","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] ALTERA, Stratix II Architecture, Altera, San Jose, CA, 2005."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] J.H. Anderson and Q. Wang, \u201cArea-efficient FPGA logic elements: Architecture and synthesis,\u201d Proc. 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp.369-375, 2011.","DOI":"10.1109\/ASPDAC.2011.5722215"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Z. Zilic and Z.G. Vranesic, \u201cUsing decision diagrams to design ULMs for FPGAs,\u201d IEEE Trans. Comput., vol.47, no.9, pp.971-982, Sept. 1998.","DOI":"10.1109\/12.713316"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] M. Iida, M. Amagasaki, Y. Okamoto, Q. Zhao, and T. Sueyoshi, \u201cCOGRE: A novel compact logic cell architecture for area minimization,\u201d IEICE Trans. Inf. & Syst., vol.E95-D, no.2, pp.294-302, 2012.","DOI":"10.1587\/transinf.E95.D.294"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Q. Zhao, K. Yanagida, M. Amagasaki, M. Iida, M. Kuga, and T. Sueyoshi, \u201cA logic cell architecture exploiting the Shannon expansion for the reduction of configuration memory,\u201d Proc. 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-6, 2014.","DOI":"10.1109\/FPL.2014.6927460"},{"key":"6","unstructured":"[6] K. McElvain, \u201cIWLS'93 benchmark set: Version 4.0,\u201d Distributed as part of the MCNC International Workshop on Logic Synthesis '93 Benchmark Distribution, 1993."},{"key":"7","unstructured":"[7] V. Bets, http:\/\/www.spec.org\/osg\/cpu2000\/CINT2000\/175.vpr\/docs\/175.vpr.html"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, \u201cCombinational and sequential mapping with priority cuts,\u201d Proc. IEEE\/ACM International Conference on Computer-Aided Design, pp.354-361, 2007.","DOI":"10.1109\/ICCAD.2007.4397290"},{"key":"9","unstructured":"[9] Berkeley Logic Synthesis and Verification Group, \u201cABC: A System for Sequential Synthesis and Verification.\u201d"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] D. Chai and A. Kuehlmann, \u201cBuilding a better Boolean matcher and symmetry detector,\u201d Proc. Design Automation & Test in Europe Conference, pp.1-6, 2006.","DOI":"10.1109\/DATE.2006.243959"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] J. Cong, C. Wu, and Y. Ding, \u201cCut ranking and pruning: Enabling a general and efficient FPGA mapping solution,\u201d Proc. 1999 ACM\/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA'99, pp.29-35, 1999.","DOI":"10.1145\/296399.296425"},{"key":"12","unstructured":"[12] A. Mishchenko, S. Chatterjee, and R. Brayton, \u201cFast Boolean matching for LUT structures,\u201d ERL Technical Report, EECS Dept., UC Berkeley, 2007."},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] E. Ahmed and J. Rose, \u201cThe effect of LUT and cluster size on deep-submicron FPGA performance and density,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst., vol.12, no.3, pp.288-298, April 2004.","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"14","unstructured":"[14] L. Jason, B. Vaughn, C. Ted, F.W. Mark, J. Peter, K. Ian, M. Alexander, Y. Andy, and R. Jonathon, \u201cThe verilog-to-routing (VTR) project for FPGAs.\u201d"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E99.A\/12\/E99.A_2500\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,15]],"date-time":"2019-09-15T23:54:51Z","timestamp":1568591691000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transfun\/E99.A\/12\/E99.A_2500\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":14,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.e99.a.2500","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"value":"0916-8508","type":"print"},{"value":"1745-1337","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}