{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T10:39:24Z","timestamp":1648723164932},"reference-count":12,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"9","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2014]]},"DOI":"10.1587\/transinf.2013lop0024","type":"journal-article","created":{"date-parts":[[2014,8,31]],"date-time":"2014-08-31T23:32:28Z","timestamp":1409527948000},"page":"2304-2311","source":"Crossref","is-referenced-by-count":2,"title":["Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip"],"prefix":"10.1587","volume":"E97.D","author":[{"given":"Akira","family":"MOCHIZUKI","sequence":"first","affiliation":[{"name":"Research Institute of Electrical Communication, Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hirokatsu","family":"SHIRAHAMA","sequence":"additional","affiliation":[{"name":"Research Institute of Electrical Communication, Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuma","family":"WATANABE","sequence":"additional","affiliation":[{"name":"Research Institute of Electrical Communication, Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takahiro","family":"HANYU","sequence":"additional","affiliation":[{"name":"Research Institute of Electrical Communication, Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] S. Vangal, et al., \u201cAn 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS,\u201d IEEE International Solid-State Circuits Conference (ISSCC 2007), Digest of Technical Papers, pp.98-99, 589, Feb. 2007.","DOI":"10.1109\/ISSCC.2007.373606"},{"key":"2","unstructured":"[2] D.M. Chapiro, Globally-asynchronous locally-synchronous systems, Ph.D. dissertation, Stanford University, Stanford, CA, Oct. 1984."},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] D. Lattard, E. Beigne, F. Clermidy, Y. Durand, R. Lemaire, P. Vivet, and F. Berens, \u201cA reconfigurable baseband platform based on an asynchronous network-on-chip,\u201d IEEE J. Solid-State Circuits, vol.1, no.43, pp.223-235, 2008.","DOI":"10.1109\/JSSC.2007.909339"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] A. Banerjee, P.T. Wolkotte, R.D. Mullins, S.W. Moore, and G.J.M. Smit, \u201cAn energy and performance exploration of network-on-chip architectures,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.17, pp.319-329, 2009.","DOI":"10.1109\/TVLSI.2008.2011232"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] F. Clermidy, C. Bernard, R. Lemaire, J. Martin, I. Miro-Panades, Y. Thonnart, P. Vivet, and N. Wehn, \u201cA 477mW NoC-based digital baseband for MIMO 4G SDR,\u201d IEEE International Solid-State Circuits Conference (ISSCC 2010), Digest of Technical Papers, pp.278-279, Feb. 2010.","DOI":"10.1109\/ISSCC.2010.5433920"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] P.T. Wolkotte, P.K.F. Holzenspies, and G.J.M. Smit, \u201cFast, accurate and detailed NoC simulations,\u201d First International Symposium on Networks-on-Chip (NOCS 2007), pp.323-332, 2007.","DOI":"10.1109\/NOCS.2007.18"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] S. Lotlikar, V. Pai, and P.V. Gratz, \u201cAcENoCs: A configurable HW\/SW platform for FPGA accelerated NoC emulation,\u201d 24th Annual Conference on VLSI Design, pp.147-152, 2011.","DOI":"10.1109\/VLSID.2011.46"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] N. Onizawa, T. Funazaki, A. Matsumoto, and T. Hanyu, \u201cAccurate asynchronous network-on-chip simulation based on a delay-aware model,\u201d IEEE Annual Symposium on VLSI (ISVLSI 2010), pp.357-362, July 2010.","DOI":"10.1109\/ISVLSI.2010.45"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] T. Hanyu, Y. Watanabe, and A. Matsumoto, \u201cAccurate and high-speed asynchronous network-on-chip simulation using physical wire-delay information,\u201d 43rd IEEE International Symposium on Multiple-Valued Logic, pp.266-271, May 2013.","DOI":"10.1109\/ISMVL.2013.11"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] W.J. Dally and C.L. Seitz, \u201cDeadlock-free message routing in multiprocessor interconnection networks,\u201d IEEE Trans. Comput., vol.C-36, no.5, pp.547-553, 1987.","DOI":"10.1109\/TC.1987.1676939"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] T. Verhoff, \u201cDelay-insensitive codes; An overview,\u201d Distributed Computing, vol.3, pp.1-8, 1987.","DOI":"10.1007\/BF01788562"},{"key":"12","unstructured":"[12] LVDS Owner's Manual, National Semiconductor, 4th ed., 2008."}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E97.D\/9\/E97.D_2013LOP0024\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,26]],"date-time":"2021-04-26T06:10:39Z","timestamp":1619417439000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E97.D\/9\/E97.D_2013LOP0024\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014]]},"references-count":12,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2014]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2013lop0024","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014]]}}}