{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T14:07:33Z","timestamp":1648562853034},"reference-count":7,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2015]]},"DOI":"10.1587\/transinf.2014edl8171","type":"journal-article","created":{"date-parts":[[2015,1,31]],"date-time":"2015-01-31T17:09:47Z","timestamp":1422724187000},"page":"433-436","source":"Crossref","is-referenced-by-count":0,"title":["A Load-Balanced Deterministic Runtime for Pipeline Parallelism"],"prefix":"10.1587","volume":"E98.D","author":[{"given":"Chen","family":"CHEN","sequence":"first","affiliation":[{"name":"School of Computer, National University of Defense Technology"},{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kai","family":"LU","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology"},{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoping","family":"WANG","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology"},{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xu","family":"ZHOU","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology"},{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhendong","family":"WU","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology"},{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] C. Bienia, S. Kumar, J.P. Singh, and K. Li, \u201cThe PARSEC benchmark suite: Characterization and architectural implications,\u201d Proc. Intl Conf. Parallel Architectures and Compilation Techniques, PACT, pp.72-81, 2008.","DOI":"10.1145\/1454115.1454128"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] M. Olszewski, J. Ansel, and S. Amarasinghe, \u201cKendo: Efficient deterministic multithreading in software,\u201d Proc. 14th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.97-108, 2009.","DOI":"10.1145\/1508244.1508256"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] K. Lu, X. Zhou, T. Bergan, and X. Wang, \u201cEfficient deterministic multithreading without global barriers,\u201d Proc. PPOPP, pp.287-300, 2014.","DOI":"10.1145\/2692916.2555252"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] H. Cui, J. Simsa, Y.-H. Lin, H. Li, B. Blum, X. Xu, J. Yang, G.A. Gibson, and R.E. Bryant, \u201cParrot: A practical runtime for deterministic, stable, and reliable threads,\u201d Proc. Twenty-Fourth ACM Symposium on Operating Systems Principles, pp.388-405, 2013.","DOI":"10.1145\/2517349.2522735"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] T. Liu, C. Curtsinger, and E.D. Berger, \u201cDTHREADS: Efficient deterministic multithreading,\u201d Proc. 22nd ACM Symposium on Operating Systems Principles, pp.327-336, 2011.","DOI":"10.1145\/2043556.2043587"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] T. Merryfield and J. Eriksson, \u201cConversion: Multi-version concurrency control for main memory segments,\u201d Proc. EuroSys, pp.127-139, 2013.","DOI":"10.1145\/2465351.2465365"},{"key":"7","unstructured":"[7] Intel, Source code for Intel threading building blocks, http:\/\/www.threadingbuildingblocks.org\/, 2009."}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E98.D\/2\/E98.D_2014EDL8171\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,20]],"date-time":"2019-08-20T07:47:45Z","timestamp":1566287265000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E98.D\/2\/E98.D_2014EDL8171\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"references-count":7,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2015]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2014edl8171","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015]]}}}