{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,13]],"date-time":"2025-05-13T22:10:07Z","timestamp":1747174207586,"version":"3.40.5"},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2014]]},"DOI":"10.1587\/transinf.2014edp7177","type":"journal-article","created":{"date-parts":[[2014,11,30]],"date-time":"2014-11-30T23:30:16Z","timestamp":1417390216000},"page":"3110-3123","source":"Crossref","is-referenced-by-count":1,"title":["MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism"],"prefix":"10.1587","volume":"E97.D","author":[{"given":"Yuya","family":"KORA","sequence":"first","affiliation":[{"name":"Department of Computational Science and Engineering, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyohei","family":"YAMAGUCHI","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideki","family":"ANDO","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, Nagoya University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] N.P. Jouppi, \u201cImproving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers,\u201d Proc. 17th Annual International Symposium on Computer Architecture, pp.364-373, May 1990.","DOI":"10.1145\/325096.325162"},{"key":"2","unstructured":"[2] J.L. Baer and T.F. Chen, \u201cAn effective on-chip preloading scheme to reduce data access penalty,\u201d Proc. 1991 Conference on Supercomputing, pp.176-186, Nov. 1991."},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Y. Chou, \u201cLow-cost epoch-based correlation prefetching for commercial applications,\u201d Proc. 40th Annual International Symposium on Microarchitecture, pp.301-313, Dec. 2007.","DOI":"10.1109\/MICRO.2007.4408264"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] J.E. Smith and A.R. Pleszkun, \u201cImplementation of precise interrupts in piplined processors,\u201d Proc. 12th Annual International Symposium on Computer Architecture, pp.291-299, June 1985.","DOI":"10.1145\/285930.285988"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] R.M. Tomasulo, \u201cAn efficient algorithm for exploiting multiple arithmetic units,\u201d IBM Journal of Research and Development, vol.11, no.1, pp.25-33, Jan. 1967.","DOI":"10.1147\/rd.111.0025"},{"key":"6","unstructured":"[6] Intel, P6 Family of Processors-Hardware Developer&apos;s Manual, Sept. 1998."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Y. Kora, K. Yamaguchi, and H. Ando, \u201cMLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP,\u201d Proc. 46th Annual International Symposium on Microarchitecture, pp.37-48, Dec. 2013.","DOI":"10.1145\/2540708.2540713"},{"key":"8","unstructured":"[8] M. Johnson, Superscalar microprocessor design, Prentice Hall, Inc., Engliwood Cliffs, New Jersey, USA, 1991."},{"key":"9","unstructured":"[9] H. Ando, Instruction-Level Parallel Processing-Processor Architecture and Compilers-, Corona Publishing Co., Ltd., Tokyo, Japan, 2005."},{"key":"10","unstructured":"[10] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, San Francisco, California, USA, 2011."},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] O. Mutlu, J. Stark, C. Wilkerson, and Y.N. Patt, \u201cRunahead execution: An effective alternative to large instruction windows,\u201d Proc. Nineth Annual International Symposium on High-Performance Computer Architecture, pp.129-140, Feb. 2003.","DOI":"10.1109\/MM.2003.1261383"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] S. Chaudhry, R. Cypher, M. Ekman, M. Karlsson, A. Landin, S. Yip, H. Zeffer, and M. Tremblay, \u201cRock: A high-performance Sparc CMT processor,\u201d IEEE Micro, vol.29, no.2, pp.6-16, March\/April 2009.","DOI":"10.1109\/MM.2009.34"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] H.Q. Le, W.J. Starke, J.S. Fields, F.P. O&apos;Connell, D.Q. Nguyen, B.J. Ronchetti, W.M. Sauer, E.M. Schwarz, and M.T. Vaden, \u201cIBM POWER6 microarchitecture,\u201d IBM Journal of Research and Development, vol.51, no.6, pp.639-662, Nov. 2007.","DOI":"10.1147\/rd.516.0639"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] K. Yamaguchi, Y. Kora, and H. Ando, \u201cEvaluation of issue queue delay: Banking tag RAM and identifying correct critical path,\u201d Proc. 29th International Conference on Computer Design, pp.313-319, Oct. 2011.","DOI":"10.1109\/ICCD.2011.6081417"},{"key":"15","unstructured":"[15] http:\/\/www.mosis.com\/"},{"key":"16","unstructured":"[16] http:\/\/www.eas.asu.edu\/~ptm\/"},{"key":"17","unstructured":"[17] N. Muralimanohar, R. Balasubramonian, and N.P. Jouppi, \u201cCACTI 6.0: A tool to model large caches,\u201d HPL-2009-85, HP Laboratories, April 2009."},{"key":"18","unstructured":"[18] http:\/\/www.simplescalar.com\/"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] S. Li, J.H. Ahn, R.D. Strong, J.B. Brockman, D.M. Tullsen, and N.P. Jouppi, \u201cMcPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures,\u201d Proc. 42nd Annual International Symposium on Microarchitecture, pp.469-480, Dec. 2009.","DOI":"10.1145\/1669112.1669172"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] M. Yuffe, M. Mehalel, E.K.J. Shor, T. Kurts, E. Altshuler, E. Fayneh, K. Luria, and M. Zelikson, \u201cA fully integrated multi-CPU, processor graphics, and memory controller 32-nm processor,\u201d IEEE J. Solid-State Circuits, vol.47, pp.194-205, Jan. 2012.","DOI":"10.1109\/JSSC.2011.2167814"},{"key":"21","unstructured":"[21] F. Pollack, \u201cNew microarchitecture challenges in the coming generations of CMOS process technologies,\u201d Proc. 32nd Annual International Symposium on Microarchitecture, Nov. 1999."},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] A. Cristal, O.J. Santana, F. Cazorla, M. Galluzzi, T. Ram\u00edrez, M. Peric\u00e0s, and M. Valero, \u201cKilo-instruction processors: Overcoming the memory wall,\u201d IEEE Micro, vol.25, no.3, pp.48-57, May\/June 2005.","DOI":"10.1109\/MM.2005.53"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] D.H. Albonesi, R. Balasubramonian, S.G. Dropsho, S. Dwarkadas, E.G. Friedman, M.C. Huang, V. Kursun, G. Magklis, M.L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P.W. Cook, and S.E. Schuster, \u201cDynamically tuning processor resources with adaptive processing,\u201d Computer, vol.36, pp.49-58, Dec. 2003.","DOI":"10.1109\/MC.2003.1250883"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] D. Ponomarev, G. Kucuk, and K. Ghose, \u201cReducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources,\u201d Proc. 34th Annual International Symposium on Microarchitecture, pp.90-101, Dec. 2001.","DOI":"10.1109\/MICRO.2001.991108"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] D. Folegnani and A. Gonz\u00e1lez, \u201cEnergy-effective issue logic,\u201d Proc. 28th Annual International Symposium on Computer Architecture, pp.230-239, June 2001.","DOI":"10.1145\/384285.379266"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] A.R. Lebeck, J. Koppanalil, T. Li, J. Patwardhan, and E. Rotenberg, \u201cA large, fast instruction window for tolerating cache misses,\u201d Proc. 29th Annual International Symposium on Computer Architecture, pp.59-70, May 2002.","DOI":"10.1145\/545214.545223"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] J.A. Farrell and T.C. Fischer, \u201cIssue logic for a 600-MHz out-of-order execution microprocessor,\u201d IEEE J. Solid-State Circuits, vol.33, no.5, pp.707-712, May 1998.","DOI":"10.1109\/4.668985"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] S.T. Srinivasan, R. Rajwar, H. Akkary, A. Gandhi, and M. Upton, \u201cContinual flow pipelines,\u201d Proc. 11th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.107-119, Oct. 2004.","DOI":"10.1145\/1037187.1024407"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] E. Brekelbaum, J. Rupley, C. Wilkerson, and B. Black, \u201cHierarchical scheduling windows,\u201d Proc. 35th Annual International Symposium on Microarchitecture, pp.27-36, Nov. 2002.","DOI":"10.1109\/MICRO.2002.1176236"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] A. Yamamoto, Y. Tanaka, H. Ando, and T. Shimada, \u201cData prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation,\u201d Proc. Eighth Workshop on Memory Performance: Dealing with Applications, Systems and Architectures, pp.41-48, Sept. 2007.","DOI":"10.1145\/1327171.1327175"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] A. Yamamoto, Y. Tanaka, H. Ando, and T. Shimada, \u201cTwo-step physical register deallocation for data prefetching and address pre-calculation,\u201d IPSJ Trans. Advanced Computing Systems, vol.1, no.2, pp.34-46, Aug. 2008.","DOI":"10.2197\/ipsjtrans.1.94"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] Y. Tanaka and H. Ando, \u201cReducing register file size through instruction pre-execution enhanced by value prediction,\u201d Proc. 27th IEEE International Conference on Computer Design, pp.238-245, Oct. 2009.","DOI":"10.1109\/ICCD.2009.5413149"},{"key":"33","unstructured":"[33] Y. Tanaka and H. Ando, \u201cRegister file size reduction through instruction pre-execution incorporating value prediction,\u201d IEICE Trans. Inf. &amp; Syst., vol.E93-D, no.12, pp.3294-3305, Dec. 2010."}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E97.D\/12\/E97.D_2014EDP7177\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,13]],"date-time":"2025-05-13T21:51:54Z","timestamp":1747173114000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E97.D\/12\/E97.D_2014EDP7177\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014]]},"references-count":33,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2014]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2014edp7177","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"type":"print","value":"0916-8532"},{"type":"electronic","value":"1745-1361"}],"subject":[],"published":{"date-parts":[[2014]]}}}