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Scott, G. Faanes, J. Schwarzmeier, E. Lundberg, T. Johnson, M. Bye, and G. Schwoerer, \u201cThe cray blackwidow: A highly scalable vector multiprocessor,\u201d SC'07: Proc. 2007 ACM\/IEEE Conference on Supercomputing, pp.1-12, 2007."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec, \u201cTarantula: A vector extension to the alpha architecture,\u201d Proc. 29th Annual International Symposium on Computer Architecture, pp.281-292, 2002.","DOI":"10.1145\/545214.545247"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] C. Batten, R. Krashinsky, S. Gerding, and K. Asanovic, \u201cCache refill\/access decoupling for vector machines,\u201d MICRO 37: Proc. 37th Annual IEEE\/ACM International Symposium on Microarchitecture, pp.331-342, 2004.","DOI":"10.1109\/MICRO.2004.9"},{"key":"9","unstructured":"[9] A. Shahbahrami, B. Juurlink, and S. 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