{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:37:40Z","timestamp":1765355860498,"version":"3.40.5"},"reference-count":24,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2014]]},"DOI":"10.1587\/transinf.2014pap0015","type":"journal-article","created":{"date-parts":[[2014,11,30]],"date-time":"2014-11-30T23:30:16Z","timestamp":1417390216000},"page":"3072-3082","source":"Crossref","is-referenced-by-count":6,"title":["ILP Based Multithreaded Code Generation for Simulink Model"],"prefix":"10.1587","volume":"E97.D","author":[{"given":"Kai","family":"HUANG","sequence":"first","affiliation":[{"name":"Institute of VLSI Design, Zhejiang University"}]},{"given":"Min","family":"YU","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Zhejiang University"}]},{"given":"Xiaomeng","family":"ZHANG","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Zhejiang University"}]},{"given":"Dandan","family":"ZHENG","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Zhejiang University"}]},{"given":"Siwen","family":"XIU","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Zhejiang University"}]},{"given":"Rongjie","family":"YAN","sequence":"additional","affiliation":[{"name":"Laboratory of Computer Science, Institute of Software Chinese Academy of Sciences"}]},{"given":"Kai","family":"HUANG","sequence":"additional","affiliation":[{"name":"Department of Informatics VI, Technical University of Munich"}]},{"given":"Zhili","family":"LIU","sequence":"additional","affiliation":[{"name":"Hangzhou C-SKY Co. Ltd"}]},{"given":"Xiaolang","family":"YAN","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Zhejiang University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] S.I. Han, S.I. Chae, L. Brisolara, L. Carro, R. Reis, X. Guerin, and A.A. Jerraya, \u201cMemory-effient multithreaded code generation from simulink for heterogeneous mpsoc,\u201d Design Automation for Embedded Systems, vol.11, no.4, pp.249-283, 2007.","DOI":"10.1007\/s10617-007-9009-4"},{"key":"2","unstructured":"[2] G. Kahn and D. MacQueen, \u201cCoroutines and networks of parallel processes,\u201d 1976."},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] E.A. Lee and T.M. Parks, \u201cDataflow process networks,\u201d Proc. IEEE, vol.83, no.5, pp.773-801, 1995.","DOI":"10.1109\/5.381846"},{"key":"4","unstructured":"[4] Simulink, Mathworks. http:\/\/www.mathworks.com"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] L. Thiele, I. Bacivarov, W. Haid, and K. Huang, \u201cMapping applications to tiled multiprocessor embedded systems,\u201d Seventh International Conference on Application of Concurrency to System Design, 2007. ACSD 2007. pp.29-40, 2007.","DOI":"10.1109\/ACSD.2007.53"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] S. Kwon, Y. Kim, W.C. Jeun, S. Ha, and Y. Paek, \u201cA retargetable parallel-programming framework for mpsoc,\u201d ACM Trans. Design Automation of Electronic Systems (TODAES), vol.13, no.3, p.39, 2008.","DOI":"10.1145\/1367045.1367048"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] J. Castrillon, R. Velasquez, A. Stulova, W. Sheng, J. Ceng, R. Leupers, G. Ascheid, and H. Meyr, \u201cTrace-based kpn composability analysis for mapping simultaneous applications to mpsoc platforms,\u201d Proc. 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ED&amp;TC 96. pp.275-281, 1996.","DOI":"10.1109\/EDTC.1996.494313"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Y. Yi, W. Han, X. Zhao, A.T. Erdogan, and T. Arslan, \u201cAn ilp formulation for task mapping and scheduling on multi-core architectures,\u201d Design, Automation &amp; Test in Europe Conference &amp; Exhibition, 2009. DATE&apos;09., pp.33-38, 2009.","DOI":"10.1109\/DATE.2009.5090629"},{"key":"18","unstructured":"[18] S.I. Han, S.I. Chae, and A.A. Jerraya, \u201cFunctional modeling techniques for effcient sw code generation of video codec applications,\u201d Proc. 2006 Asia and South Pacific Design Automation Conference, pp.935-940, 2006."},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] K. Huang, S.i. Han, K. Popovici, L. Brisolara, X. Guerin, L. Li, X. Yan, S.l. Chae, L. Carro, and A.A. Jerraya, \u201cSimulink-based mpsoc design flow: case study of motion-jpeg and h. 264,\u201d Design Automation Conference, 2007. DAC&apos;07. 44th ACM\/IEEE, pp.39-42, 2007.","DOI":"10.1109\/DAC.2007.375049"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] S.I. Han, S.I. Chae, L. Brisolara, L. Carro, K. Popovici, X. Guerin, A.A. Jerraya, K. Huang, L. Li, and X. Yan, \u201cSimulink-based heterogeneous multiprocessor soc design flow for mixed hardware\/software refinement and simulation,\u201d Integration, the VLSI Journal, vol.42, no.2, pp.227-245, 2009.","DOI":"10.1016\/j.vlsi.2008.08.003"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] S.I. Han, X. Guerin, S.I. Chae, and A.A. Jerraya, \u201cBuffer memory optimization for video codec application modeled in simulink,\u201d Proc. 43rd Annual Design Automation Conference, pp.689-694, 2006.","DOI":"10.1145\/1146909.1147084"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] L. Brisolara, S.i. Han, X. Guerin, L. Carro, R. Reis, S.I. Chae, and A. Jerraya, \u201cReducing fine-grain communication overhead in multithread code generation for heterogeneous mpsoc,\u201d Proc. 10th International Workshop on Software &amp; Compilers for Embedded Systems, pp.81-89, 2007.","DOI":"10.1145\/1269843.1269855"},{"key":"23","unstructured":"[23] C-SKY Inc. http:\/\/www.c-sky.com."},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] S.I. Han, A. Baghdadi, M. Bonaciu, S.I. Chae, and A.A. Jerraya, \u201cAn effcient scalable and flexible data transfer architecture for multiprocessor soc with massive distributed memory,\u201d Proc. 41st Annual Design Automation Conference, pp.250-255, 2004.","DOI":"10.1145\/996566.996636"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E97.D\/12\/E97.D_2014PAP0015\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,13]],"date-time":"2025-05-13T21:51:51Z","timestamp":1747173111000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E97.D\/12\/E97.D_2014PAP0015\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014]]},"references-count":24,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2014]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2014pap0015","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"type":"print","value":"0916-8532"},{"type":"electronic","value":"1745-1361"}],"subject":[],"published":{"date-parts":[[2014]]}}}