{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T09:24:50Z","timestamp":1775467490987,"version":"3.50.1"},"reference-count":21,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/transinf.2016awi0005","type":"journal-article","created":{"date-parts":[[2017,3,31]],"date-time":"2017-03-31T22:23:52Z","timestamp":1490999032000},"page":"633-644","source":"Crossref","is-referenced-by-count":2,"title":["Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core"],"prefix":"10.1587","volume":"E100.D","author":[{"given":"Motoki","family":"AMAGASAKI","sequence":"first","affiliation":[{"name":"Graduate School of Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuki","family":"NISHITANI","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazuki","family":"INOUE","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiro","family":"IIDA","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Morihiro","family":"KUGA","sequence":"additional","affiliation":[{"name":"Faculty of Advanced Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshinori","family":"SUEYOSHI","sequence":"additional","affiliation":[{"name":"Faculty of Advanced Science and Technology, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J.A. Cheatham, J.M. Emmert, and S. Baumgart, \u201cA survey of fault tolerant methodologies for FPGAs,\u201d ACM Trans. Design Automation of Electronic Systems (TODAES), vol.11, no.2, pp.501-533, 2006.","DOI":"10.1145\/1142155.1142167"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] M. Amagasaki, Q. Zhao, M. Iida, M. Kuga, and T. Sueyoshi, \u201cFault-tolerant FPGA: Architectures and design for programmable logic intellectual property core in SoC,\u201d IEICE Trans. Inf. &amp; Syst., vol.E98-D, no.2, pp.252-261, Feb. 2015.","DOI":"10.1587\/transinf.2014RCP0009"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] E. Stott, P. Sedcole, and P.Y.K. Cheung, \u201cFault tolerant methods for reliability in FPGAs,\u201d Proc. International Conference on Field Programmable Logic and Applications, pp.415-420, Sept. 2008,","DOI":"10.1109\/FPL.2008.4629973"},{"key":"4","unstructured":"[4] A. Doumar and H. Ito, \u201cDefect and fault tolerance SRAM-based FPGAs by shifting the configuration data,\u201d IEICE Trans. Inf. &amp; Syst., vol.E83-D, no.5, pp.1104-1115, May 2000."},{"key":"5","unstructured":"[5] J.L. Kelly and P.A. Ivey, \u201cA novel approach to defect tolerant design for SRAM based FPGAs,\u201d Proc. ACM International Workshop on Field Programmable Gate Arrays, pp.1-11, Feb. 1994."},{"key":"6","unstructured":"[6] S. Durand and C. Piguet, \u201cFPGA with selfrepair capabilities,\u201d Proc. ACM International Workshop on Field Programmable Gate Arrays, pp.1-6, Feb. 1994."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] N. Howard, A. Tyrrell, and N. Allinson, \u201cThe yield enhancement of field-programmable gate arrays,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.2, no.1, pp.115-123, 1994.","DOI":"10.1109\/92.273147"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] V. Lakamraju and R. Tessier, \u201cTolerating operational faults in cluster-based FPGAs,\u201d Proc. ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, pp.187-194, 2000.","DOI":"10.1145\/329166.329205"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] F. Lima, L. Carro, and R. Reis, \u201cDesigning fault tolerant systems into SRAM-based FPGAs,\u201d Proc. 40th Annual Design Automation Conference, pp.650-655, 2003.","DOI":"10.1145\/775832.775997"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S. Srinivasan, P. Mangalagiri, Y. Xie, N. Vijaykrishnan, and K. Sarpatwari, \u201cFLAW: FPGA lifetime awareness,\u201d Proc. 43th Annual Design Automation Conference, pp.630-635, 2006.","DOI":"10.1145\/1146909.1147070"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] M. Yabuuchi and K. Kobayashi, \u201cNBTI-induced delay degradation analysis of FPGA routing structures,\u201d IPSJ Trans. System LSI Design Methodology, vol.5, pp.143-149, 2012.","DOI":"10.2197\/ipsjtsldm.5.143"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] K. Kyiakoulakos and D. Pnevmatikatos, \u201cA novel SRAM-based FPGA architecture for efficient TMR fault tolerance support,\u201d Proc. International Conference on Field Programmable Logic and Applications (FPL), pp.193-198, Sept. 2009.","DOI":"10.1109\/FPL.2009.5272319"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] C. Bolchini, A. Miele, and M.D. Satambrogio, \u201cTMR and partial dynamic reconfiguration to mitigate SEU faults in FPGAs,\u201d Proc. IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), pp.87-95, Sept. 2007.","DOI":"10.1109\/DFT.2007.25"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] I. Kuon, R. Tessier, and J. Rose, \u201cFPGA architecture: Survey and challenges,\u201d Foundations and Trends in Electronic Design Automation, vol.2, no.2, pp.135-253, Feb. 2007.","DOI":"10.1561\/1000000005"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] Q. Zhao, Y. Ichinomiya, Y. Okamoto, M. Amagasaki, M. Iida, and T. Sueyoshi, \u201cA robust reconfigurable logic device based on less configuration memory logic cell,\u201d Proc. International Conference on Field-Programmable Technology (FPT), pp.162-169, Dec. 2010.","DOI":"10.1109\/FPT.2010.5681775"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] K. Inoue, M. Koga, M. Amagasaki, M. Iida, Y. Ichida, M. Saji, J. Iida, and T. Sueyoshi, \u201cAn easily testable routing architecture and prototype chip,\u201d IEICE Trans. Inf. &amp; Syst., vol.E95-D, no.2, pp.303-313, Feb. 2012.","DOI":"10.1587\/transinf.E95.D.303"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W.M. Fang, and J. Rose, \u201cVPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling,\u201d Proc. ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, pp.133-142, Feb. 2009.","DOI":"10.1145\/1508128.1508150"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] G.G. Lemieux and D.M. Lewis, \u201cAnalytical framework for switch block design,\u201d Proc. FPL, pp.122-131, Aug. 2002.","DOI":"10.1007\/3-540-46117-5_14"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for deepsubmicron FPGAs, Kluwer Academic, 1999.","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"20","unstructured":"[20] K. McElvain, \u201cIWLS&apos;93 benchmark set: Version 4.0,\u201d Distributed as part of the MCNC International Workshop on Logic Synthesis&apos;93 benchmark distribution, May 1993."},{"key":"21","unstructured":"[21] \u201cABC: A system for sequential synthesis and verification,\u201dhttp:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/4\/E100.D_2016AWI0005\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,20]],"date-time":"2019-09-20T13:50:10Z","timestamp":1568987410000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/4\/E100.D_2016AWI0005\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":21,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016awi0005","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}