{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,21]],"date-time":"2026-01-21T04:56:09Z","timestamp":1768971369787,"version":"3.49.0"},"reference-count":39,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/transinf.2016edp7205","type":"journal-article","created":{"date-parts":[[2016,12,31]],"date-time":"2016-12-31T22:21:48Z","timestamp":1483222908000},"page":"79-90","source":"Crossref","is-referenced-by-count":3,"title":["ARW: Efficient Replacement Policies for Phase Change Memory and NAND Flash"],"prefix":"10.1587","volume":"E100.D","author":[{"given":"Xi","family":"ZHANG","sequence":"first","affiliation":[{"name":"Key Laboratory of Trustworthy Distributed Computing and Service of Ministry of Education, Beijing University of Post and Telecommunications"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinning","family":"DUAN","sequence":"additional","affiliation":[{"name":"Key Laboratory of Trustworthy Distributed Computing and Service of Ministry of Education, Beijing University of Post and Telecommunications"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jincui","family":"YANG","sequence":"additional","affiliation":[{"name":"Key Laboratory of Trustworthy Distributed Computing and Service of Ministry of Education, Beijing University of Post and Telecommunications"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jingyuan","family":"WANG","sequence":"additional","affiliation":[{"name":"School of Computer Science and Engineering, Beihang University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] X. Zhang, Q. Hu, D. Wang, C. Li, and H. Wang, \u201cA read-write aware replacement policy for phase change memory,\u201d International Workshop on Advanced Parallel Processing Technologies, pp.31-45, Springer, 2011.","DOI":"10.1007\/978-3-642-24151-2_3"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] R. Bez and A. Pirovano, \u201cNon-volatile memory technologies: emerging concepts and new materials,\u201d Materials Science in Semiconductor Processing, vol.7, no.4, pp.349-355, 2004.","DOI":"10.1016\/j.mssp.2004.09.127"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] X. Pan and R. Teodorescu, \u201cUsing STT-RAM to enable energy-efficient near-threshold chip multiprocessors,\u201d Proceedings of the 23rd international conference on Parallel architectures and compilation, pp.485-486, ACM, 2014.","DOI":"10.1145\/2628071.2628132"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Z. Wang, S. Shan, T. Cao, J. Gu, Y. Xu, S. Mu, Y. Xie, and D.A. Jim\u00e9nez, \u201cWADE: Writeback-aware dynamic cache management for nvm-based main memory system,\u201d ACM Transactions on Architecture and Code Optimization (TACO), vol.10, no.4, p.51, 2013.","DOI":"10.1145\/2541228.2555307"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] T. Kgil, D. Roberts, and T. Mudge, \u201cImproving nand flash based disk caches,\u201d Computer Architecture, 2008. ISCA'08. 35th International Symposium on, pp.327-338, IEEE, 2008.","DOI":"10.1109\/ISCA.2008.32"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] D. Seo and D. Shin, \u201cRecently-evicted-first buffer replacement policy for flash storage devices,\u201d IEEE Trans. Consum. Electron., vol.54, no.3, pp.1228-1235, 2008.","DOI":"10.1109\/TCE.2008.4637611"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] S. Raoux, G.W. Burr, M.J. Breitwisch, C.T. Rettner, Y.-C. Chen, R.M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung and C.H. Lam, \u201cPhase-change random access memory: A scalable technology,\u201d IBM Journal of Research and Development, vol.52, no.4.5, pp.465-479, 2008.","DOI":"10.1147\/rd.524.0465"},{"key":"8","unstructured":"[8] Intel, \u201cIntel, stmicroelectronics deliver industry's first phase change memory prototypes,\u201d 2008."},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie, \u201cHybrid cache architecture with disparate memory technologies,\u201d ACM SIGARCH computer architecture news, pp.34-45, ACM, 2009.","DOI":"10.1145\/1555754.1555761"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] M.K. Qureshi, V. Srinivasan, and J.A. Rivers, \u201cScalable high performance main memory system using phase-change memory technology,\u201d ACM SIGARCH Computer Architecture News, vol.37, no.3, pp.24-33, 2009.","DOI":"10.1145\/1555815.1555760"},{"key":"11","unstructured":"[11] Numonyx, \u201cThe basics of phase change memory technology,\u201d http:\/\/www.signallake.com\/innovation\/PhaseChangeMemory.pdf. Accessed: 2016-08-22."},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Z. Li, P. Jin, X. Su, K. Cui, and L. Yue, \u201cCCF-LRU: a new buffer replacement algorithm for flash memory,\u201d IEEE Trans. Consum. Electron., vol.55, no.3, pp.1351-1359, 2009.","DOI":"10.1109\/TCE.2009.5277999"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] D.-H. Kang, J.-H. Lee, J. Kong, D. Ha, J. Yu, C.Y. Um, J.H. Park, F. Yeung, J.H. Kim, W.I. Park, Y.J. Jeon, M.K. Lee, Y.J. Song, J.H. Oh, G.T. Jeong and H.S. Jeong, \u201cTwo-bit cell operation in diode-switch phase change memory cells with 90nm technology,\u201d 2008 Symposium on VLSI Technology, pp.98-99, IEEE, 2008.","DOI":"10.1109\/VLSIT.2008.4588577"},{"key":"14","unstructured":"[14] T. UltraSPARC, \u201cSupplement to the UltraSPARC architecture 2007,\u201d 2006."},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] M.K. Qureshi, A. Jaleel, Y.N. Patt, S.C. Steely, and J. Emer, \u201cAdaptive insertion policies for high performance caching,\u201d ACM SIGARCH Computer Architecture News, pp.381-391, ACM, 2007.","DOI":"10.1145\/1273440.1250709"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] A. Jaleel, K.B. Theobald, S.C. Steely Jr, and J. Emer, \u201cHigh performance cache replacement using re-reference interval prediction (RRIP),\u201d ACM SIGARCH Computer Architecture News, pp.60-71, ACM, 2010.","DOI":"10.1145\/1816038.1815971"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] X. Zhang, L. Chongmin, L. Zhenyu, W. Haixia, W. Dongsheng, and T. Ikenaga, \u201cA novel cache replacement policy via dynamic adaptive insertion and re-reference prediction,\u201d IEICE Trans. Electron., vol.94, no.4, pp.468-476, 2011.","DOI":"10.1587\/transele.E94.C.468"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] T.J. Ham, B.K. Chelepalli, N. Xue, and B.C. Lee, \u201cDisintegrated control for energy-efficient and heterogeneous memory systems,\u201d High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on, pp.424-435, IEEE, 2013.","DOI":"10.1109\/HPCA.2013.6522338"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] M.K. Qureshi, M.M. Franceschini, and L.A. Lastras-Montano, \u201cImproving read performance of phase change memories via write cancellation and write pausing,\u201d HPCA-16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, pp.1-11, IEEE, 2010.","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] P. Zhou, B. Zhao, J. Yang, and Y. Zhang, \u201cA durable and energy efficient main memory using phase change memory technology,\u201d ACM SIGARCH computer architecture news, pp.14-23, ACM, 2009.","DOI":"10.1145\/1555754.1555759"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] P. Jin, Y. Ou, T. H\u00e4rder, and Z. Li, \u201cAD-LRU: An efficient buffer replacement algorithm for flash-based databases,\u201d Data & Knowledge Engineering, vol.72, pp.83-102, 2012.","DOI":"10.1016\/j.datak.2011.09.007"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] Y. Lv, B. Cui, B. He, and X. Chen, \u201cOperation-aware buffer management in flash-based systems,\u201d Proceedings of the 2011 ACM SIGMOD International Conference on Management of data, pp.13-24, ACM, 2011.","DOI":"10.1145\/1989323.1989326"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] R. Kalla, B. Sinharoy, W.J. Starke, and M. Floyd, \u201cPOWER7: IBM's next-generation server processor,\u201d IEEE micro, vol.30, no.2, pp.7-15, 2010.","DOI":"10.1109\/MM.2010.38"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] R. Wang, Z. Chen, N. Xiao, M. Zhang, and W. Dong, \u201cCAWR: Buffer replacement with channel-aware write reordering mechanism for ssds,\u201d ETRI Journal, vol.37, no.1, pp.147-156, 2015.","DOI":"10.4218\/etrij.15.0114.0055"},{"key":"25","unstructured":"[25] \u201cSimics full system simulator,\u201d http:\/\/www.windriver.com\/products\/simics\/. Accessed: 2016-08-22."},{"key":"26","unstructured":"[26] \u201cWisconsin multifacet gems simulator,\u201d http:\/\/www.cs.wisc.edu\/gems\/. Accessed: 2016-08-22."},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta, \u201cThe SPLASH-2 programs: Characterization and methodological considerations,\u201d ACM SIGARCH Computer Architecture News, pp.24-36, ACM, 1995.","DOI":"10.1145\/223982.223990"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] C. Bienia, S. Kumar, J.P. Singh, and K. Li, \u201cThe PARSEC benchmark suite: characterization and architectural implications,\u201d Proceedings of the 17th international conference on Parallel architectures and compilation techniques, pp.72-81, ACM, 2008.","DOI":"10.1145\/1454115.1454128"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] X. Su, P. Jin, X. Xiang, K. Cui, and L. Yue, \u201cFlash-DBSim: a simulation tool for evaluating flash-based database algorithms,\u201d Computer Science and Information Technology, 2009. ICCSIT 2009. 2nd IEEE International Conference on, pp.185-189, IEEE, 2009.","DOI":"10.1109\/ICCSIT.2009.5234967"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] M.G. Baker, J.H. Hartman, M.D. Kupfer, K.W. Shirriff, and J.K. Ousterhout, \u201cMeasurements of a distributed file system,\u201d ACM SIGOPS Operating Systems Review, pp.198-212, ACM, 1991.","DOI":"10.1145\/121133.121164"},{"key":"31","unstructured":"[31] P.B. Galvin, G. Gagne, and A. Silberschatz, Operating system concepts, John Wiley & Sons, 2013."},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] G. Dhiman, R. Ayoub, and T. Rosing, \u201cPDRAM: a hybrid pram and dram main memory system,\u201d Design Automation Conference, 2009. DAC'09. 46th ACM\/IEEE, pp.664-669, IEEE, 2009.","DOI":"10.1145\/1629911.1630086"},{"key":"33","doi-asserted-by":"crossref","unstructured":"[33] X. Wu, J. Li, L. Zhang, E. Speight, and Y. Xie, \u201cPower and performance of read-write aware hybrid caches with non-volatile memories,\u201d 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.737-742, IEEE, 2009.","DOI":"10.1109\/DATE.2009.5090762"},{"key":"34","doi-asserted-by":"crossref","unstructured":"[34] S. Cho and H. Lee, \u201cFlip-N-Write: a simple deterministic technique to improve pram write performance, energy and endurance,\u201d 2009 42nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), pp.347-357, IEEE, 2009.","DOI":"10.1145\/1669112.1669157"},{"key":"35","doi-asserted-by":"crossref","unstructured":"[35] M. Zhou, Y. Du, B. Childers, R. Melhem, and D. Moss\u00e9, \u201cWriteback-aware partitioning and replacement for last-level caches in phase change main memory systems,\u201d ACM Transactions on Architecture and Code Optimization (TACO), vol.8, no.4, pp.1-21, 2012.","DOI":"10.1145\/2086696.2086732"},{"key":"36","doi-asserted-by":"crossref","unstructured":"[36] S.M. Khan, Z. Wang, and D.A. Jimenez, \u201cDecoupled dynamic cache segmentation,\u201d IEEE International Symposium on High-Performance Comp Architecture, pp.1-12, IEEE, 2012.","DOI":"10.1109\/HPCA.2012.6169030"},{"key":"37","doi-asserted-by":"crossref","unstructured":"[37] R. Rodr\u00edguez-Rodr\u00edguez, F. Castro, D. Chaver, L. Pinuel, and F. Tirado, \u201cReducing writes in phase-change memory environments by using efficient cache replacement policies,\u201d Proceedings of the Conference on Design, Automation and Test in Europe, pp.93-96, EDA Consortium, 2013.","DOI":"10.7873\/DATE.2013.033"},{"key":"38","doi-asserted-by":"crossref","unstructured":"[38] S.-y. Park, D. Jung, J.-u. Kang, J.-s. Kim, and J. Lee, \u201cCFLRU: a replacement algorithm for flash memory,\u201d Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, pp.234-241, ACM, 2006.","DOI":"10.1145\/1176760.1176789"},{"key":"39","doi-asserted-by":"crossref","unstructured":"[39] H. Jung, H. Shim, S. Park, S. Kang, and J. Cha, \u201cLRU-WSR: integration of LRU and writes sequence reordering for flash memory,\u201d IEEE Trans. Consum. Electron., vol.54, no.3, pp.1215-1223, 2008.","DOI":"10.1109\/TCE.2008.4637609"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/1\/E100.D_2016EDP7205\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,13]],"date-time":"2025-06-13T23:43:01Z","timestamp":1749858181000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/1\/E100.D_2016EDP7205\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":39,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016edp7205","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}