{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,28]],"date-time":"2022-03-28T22:45:49Z","timestamp":1648507549936},"reference-count":32,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/transinf.2016edp7236","type":"journal-article","created":{"date-parts":[[2016,12,31]],"date-time":"2016-12-31T22:22:06Z","timestamp":1483222926000},"page":"91-106","source":"Crossref","is-referenced-by-count":0,"title":["Insufficient Vectorization: A New Method to Exploit Superword Level Parallelism"],"prefix":"10.1587","volume":"E100.D","author":[{"given":"Wei","family":"GAO","sequence":"first","affiliation":[{"name":"State Key Laboratory of Mathematical Engineering and Advanced Computing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lin","family":"HAN","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Mathematical Engineering and Advanced Computing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rongcai","family":"ZHAO","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Mathematical Engineering and Advanced Computing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yingying","family":"LI","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Mathematical Engineering and Advanced Computing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jian","family":"LIU","sequence":"additional","affiliation":[{"name":"College of Communication and Information Engineering, Nanjing University of Posts and Telecommunications"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] T. Mytkowicz and M. Marron, \u201cSingle-Core Performance is Still Relevant in the Multi-Core Era,\u201d SIMD compiling technology review[C]."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] M. Hassaballah1 and S. Omran, \u201cA Review of SIMD Multimedia Extensions and their Usage in Scientific and Engineering Applications [J],\u201d The Computer Journal, vol.51, no.6, pp.630-650, 2008.","DOI":"10.1093\/comjnl\/bxm099"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] R. Lei\u00dfa, S. Hack, and I. Wald, \u201cExtending a C-like Language for Portable SIMD Programming,\u201d Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practices of Parallel Programming (PPoPP), New Orleans, Louisiana, USA. pp.65-74, 2012.","DOI":"10.1145\/2145816.2145825"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] D. Nuzman and A. Zaks, \u201cOuter-Loop Vectorization: Revisited for Short SIMD Architectures,\u201d Proceedings of the 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.2-11, 2008.","DOI":"10.1145\/1454115.1454119"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] J. Liu, Y. Zhang, O. Jang, W. Ding, and M. Kandemir, \u201cA Compiler Framework for Extracting Superword Level Parallelism,\u201d Proceedings of the 2012 Conference on Programming Language Design and Implementation (PLDI), pp.347-358, 2012.","DOI":"10.1145\/2254064.2254106"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] V. Porpodas, A. Magni, and T.M. Jones, \u201cPSLP: Padded SLP Automatic Vectorization,\u201d Proceedings of the 2015 Annual IEEE\/ACM International Symposium on Code Generation and Optimization, 2015.","DOI":"10.1109\/CGO.2015.7054199"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] S. Kim and H. Han, \u201cEfficient SIMD Code Generation for Irregular Kernels,\u201d Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practices of Parallel Programming (PPoPP), pp.55-64, 2012.","DOI":"10.1145\/2145816.2145824"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] Y. Park, S. Seo, H. Park, H.K.Cho, and S. Mahlke, \u201cSIMD Defragmenter: Efficient ILP Realization on Data-parallel Architectures,\u201d Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp.363-374, 2012.","DOI":"10.1145\/2150976.2151014"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] A. Ramachandran, J. Vienne, R. Van Der Wijngaart, L. Koesterke, and I. Sharapov, \u201cPerformance Evaluation of NAS Parallel Benchmarks on Intel Xeon Phi,\u201d Proceedings of 42nd International Conference on Parallel Processing (ICPP), 2013.","DOI":"10.1109\/ICPP.2013.87"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] X. Liu, M. Smelyanskiy, E. Chow, and P. Dubey, \u201cEfficient Sparse Matrix-Vector Multiplication on x86-Based Many-Core Processors,\u201d Proceedings of the 2013 International Conference on Supercomputing, pp.273-282, 2013.","DOI":"10.1145\/2464996.2465013"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] X. Huo, B. Ren, and G. Agrawal, \u201cA Programming System for Xeon Phis with Runtime SIMD Parallelization,\u201d Proceedings of the 2013 International Conference on Supercomputing, pp.283-292, 2014.","DOI":"10.1145\/2597652.2597682"},{"key":"12","unstructured":"[12] R. Allen and K. Kennedy, Optimizing compilers for modern architectures, Morgan Kaufmann, 2001."},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] K. Trifunovic, D. Nuzman, A. Cohen, A. Zaks, and I. Rosen, \u201cPolyhedral-Model Guided Loop-Nest Auto-Vectorization,\u201d Proceedings of the 2009 International Conference on Parallel Architectures and Compilation Techniques (PACT), 2009.","DOI":"10.1109\/PACT.2009.18"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] M. Kong, R. Veras, K. Stock, F. Franchetti, L.-N. Pouchet, and P. Sadayappan, \u201cWhen Polyhedral Transformations Meet SIMD Code Generation,\u201d Proceedings of the 2013 Conference on Programming Language Design and Implementation (PLDI), pp.127-138, 2013.","DOI":"10.1145\/2491956.2462187"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] S. Larsen and S. Amarasinghe, \u201cExploiting superword level parallelism with multimedia instruction sets,\u201d Proc. ACM SIGPLAN Conference on Programming Language Design and Implementation, pp.145-156, June 2000.","DOI":"10.1145\/349299.349320"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] R. Barik, J. Zhao, and V. Sarkar, \u201cEfficient Selection of Vector Instructions using Dynamic Programming,\u201d Proceedings of the 43rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), 2010.","DOI":"10.1109\/MICRO.2010.38"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] J. Holewinski, R. Ramamurthi, M. Ravishankar, N. Fauzia, L.-N. Pouchet, A. Rountev, and P. Sadayappan, \u201cDynamic trace-based analysis of vectorization potential of applications,\u201d Proceedings of the Conference on Programming Language Design and Implementation (PLDI), pp.371-382, 2012.","DOI":"10.1145\/2254064.2254108"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] J. Shin, M. Hall, and J. Chame, \u201cSuperword-Level Parallelism in the Presence of Control Flow,\u201d Proceedings of the 3rd Annual IEEE\/ACM International Symposium on Code Generation and Optimization (CGO), New York, ACM Press, pp.165-175. 2005.","DOI":"10.1109\/CGO.2005.33"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] H. Tanaka, Y. Ota, N. Matsumoto, T. Hieda, Y. Takeuchi, and M. Imai, \u201cA New Compilation Technique for SIMD Code Generation across Basic Block Boundaries,\u201d Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.101-106, 2010.","DOI":"10.1109\/ASPDAC.2010.5419911"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] R. Karrenberg and S. Hack \u201cWhole-Function Vectorization,\u201d Proceedings of the 9th Annual IEEE\/ACM International Symposium on Code Generation and Optimization (CGO), 2011.","DOI":"10.1109\/CGO.2011.5764682"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] R. Kumar, A. Mart\u00ednez, and A. Gonzalez, \u201cSpeculative Dynamic Vectorization for HW\/SW Codesigned Processors,\u201d Proceedings of the 2012 International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.459-460, 2012.","DOI":"10.1145\/2370816.2370895"},{"key":"22","unstructured":"[22] M. Haque and Q. Yi, \u201cPast dependent branches through speculation,\u201d Proceedings of the 22nd International Conference on Parallel Architecture and Compilation Techniques (PACT), Washington DC: IEEE Computer Society, 2013."},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] G. Ren, P. Wu, and D. Padua, \u201cA preliminary study on the vectorization of multimedia applications for multimedia extensions,\u201d Languages and Compilers for Parallel Computing, vol.2958 of Lecture Notes in Computer Science, pp.420-435, 2004.","DOI":"10.1007\/978-3-540-24644-2_27"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] A.E. Eichenberger, P. Wu, and K. O'Brien, \u201cVectorization for SIMD architectures with alignment constraints,\u201d Proceeding of the ACM SIGPLAN 2004 conference on Programming language design and implementation (PLDI), ACM Press, New York, pp.82-93, 2004.","DOI":"10.1145\/996841.996853"},{"key":"25","unstructured":"[25] A. Shahbahrami, B. Juurlink, and S. Vassiliadis, \u201cPerformance impact of misaligned accesses in SIMD extensions,\u201d Proceedings of the 17th Annual Workshop on Circuits, Systems and Signal Processing, pp.334-342, 2006."},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] D. Nuzman, I. Rosen, and A. Zaks, \u201cAuto-vectorization of interleaved data for SIMD,\u201d Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation (PLDI), pp.132-143, 2006.","DOI":"10.1145\/1133981.1133997"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] H. Chang and W. Sung, \u201cEfficient vectorization of SIMD programs with non-aligned and irregular data access hardware,\u201d Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pp.167-176, 2008.","DOI":"10.1145\/1450095.1450121"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] G. Ren, P. Wu, and D. Padua, \u201cOptimizing data permutations for SIMD devices,\u201d Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation (PLDI), pp.118-131, 2006.","DOI":"10.1145\/1133981.1133996"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] L. Huang, L. Shen, Z. Wang, W. Shi, N. Xiao, and S. Ma, \u201cSIF: Overcoming the Limitations of SIMD Devices via Implicit Permutation,\u201d Proceedings of the 16th International Symposium on High-Performance Computer Architecture (HPCA), pp.355-366, 2010.","DOI":"10.1109\/HPCA.2010.5416631"},{"key":"30","unstructured":"[30] L. Yuxiang, S. Hui, and C. Li, \u201cVectorization-oriented local data regrouping,\u201d Computer System, vol.30, no.8, pp.1529-1534, 2009."},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] H. Fu, J. Liao, J. Yang, L. Wang, Z. Song, X. Huang, C. Yang, W. Xue, F. Liu, F. Qiao, W. Zhao, X. Yin, C. Hou, C. Zhang, W. Ge, J. Zhang, Y. Wang, C. Zhou, G. Yang, \u201cThe Sunway TaihuLight supercomputer: system and applications,\u201d Sci. China Inf. Sci., vol.59, no.7, 072001, 2016.","DOI":"10.1007\/s11432-016-5588-7"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] H. Zhou and J. Xue, \u201cA Compiler Approach for Exploiting Partial SIMD Parallelism,\u201d ACM Transactions on Architecture and Code Optimization (TACO), vol.13 no.1, April 2016.","DOI":"10.1145\/2886101"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/1\/E100.D_2016EDP7236\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,17]],"date-time":"2019-09-17T03:05:36Z","timestamp":1568689536000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/1\/E100.D_2016EDP7236\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":32,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016edp7236","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}