{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T17:48:31Z","timestamp":1760204911750},"reference-count":10,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/transinf.2016edp7397","type":"journal-article","created":{"date-parts":[[2017,6,30]],"date-time":"2017-06-30T21:41:06Z","timestamp":1498858866000},"page":"1393-1402","source":"Crossref","is-referenced-by-count":3,"title":["Reduction of Quantum Cost by Making Temporary Changes to the Function"],"prefix":"10.1587","volume":"E100.D","author":[{"given":"Nurul","family":"AIN BINTI ADNAN","sequence":"first","affiliation":[{"name":"Graduate School of Information Science and Engineering, Ritsumeikan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shigeru","family":"YAMASHITA","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Engineering, Ritsumeikan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alan","family":"MISHCHENKO","sequence":"additional","affiliation":[{"name":"Electrical and Computer Sciences University of California, Berkeley"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] S. Yamashita, S. Minato, and D.M. Miller, \u201cDDMF: An efficient decision diagram structure for design verification of quantum circuits under a practical restriction,\u201d In IEICE Trans. Fundamentals, vol.E91-A, no.12, pp.3793-3802, Dec. 2008. 10.1093\/ietfec\/e91-a.12.3793","DOI":"10.1093\/ietfec\/e91-a.12.3793"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] L.K. Grover, \u201cA fast quantum mechanical algorithm for database search,\u201d In Proceedings of the twenty-eighth annual ACM symposium on Theory of computing, pp.212-219, 1996. 10.1145\/237814.237866","DOI":"10.1145\/237814.237866"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Arabzadeh, M. Saeedi, and M.S. Zamani, \u201cRule-based optimization of reversible circuits,\u201d In Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, pp.849-854, IEEE 2010. 10.1109\/aspdac.2010.5419685","DOI":"10.1109\/ASPDAC.2010.5419684"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] K. Datta, G. Rathi, I. Sengupta, and H. Rahaman, \u201cAn improved reversible circuit synthesis approach using clustering of ESOP cubes,\u201d J. Emerg. Technol. Comput. Syst., vol.11, no.2, pp.1-16, Nov. 2014. 10.1145\/2629543","DOI":"10.1145\/2629543"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] K. Fazel, M.A. Thornton, and J.E. Rice, \u201cESOP-based Toffoli gate cascade generation,\u201d In IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp.206-209, citeseer, 2007. 10.1109\/pacrim.2007.4313212","DOI":"10.1109\/PACRIM.2007.4313212"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] N.A.B. Adnan, K. Kushida, and S. Yamashita, \u201cA pre-optimization technique to generate initial reversible circuits with low quantum cost,\u201d In IEEE International Symposium on Circuits and Systems (ISCAS), pp.2298-2301, May 2016. 10.1109\/iscas.2016.7539043","DOI":"10.1109\/ISCAS.2016.7539043"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] M. Saeedi and I.L. Markov, \u201cSynthesis and Optimization of Reversible Circuits \u2014 a survey,\u201d ACM Comput. Surv., vol.45, no.2, March 2013. 10.1145\/2431211.2431220","DOI":"10.1145\/2431211.2431220"},{"key":"8","unstructured":"[8] Z. Sasanian and D.M. Miller, \u201cReversible and quantum circuit optimization: A functional approach,\u201d In Reversible Computation 4th International Workshop, RC 2012, Copenhagen, Denmark, July 2-3, 2012, Revised Papers, vol.7581, pp.112-124, 2013. 10.1007\/978-3-642-36315-3_9"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] X. Cheng, Z. Guan, W. Wang, and L. Zhu, \u201cA simplification algorithm for reversible logic network of positive\/negative control gates,\u201d In Fuzzy Systems and Knowledge Discovery (FSKD), 2012 9th International Conference, pp.2442-2446, May 2012. 10.1109\/fskd.2012.6233837","DOI":"10.1109\/FSKD.2012.6233837"},{"key":"10","unstructured":"[10] Two-level exclusive sum-of-product minimization, http:\/\/web.cecs.pdx.edu\/~alanmi\/research\/min\/minESOP.htm."}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/7\/E100.D_2016EDP7397\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,27]],"date-time":"2019-09-27T23:33:37Z","timestamp":1569627217000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/7\/E100.D_2016EDP7397\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":10,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016edp7397","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}