{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:35:29Z","timestamp":1750221329951,"version":"3.41.0"},"reference-count":27,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/transinf.2016edp7429","type":"journal-article","created":{"date-parts":[[2017,4,30]],"date-time":"2017-04-30T22:15:09Z","timestamp":1493590509000},"page":"1035-1045","source":"Crossref","is-referenced-by-count":4,"title":["Fast Persistent Heap Based on Non-Volatile Memory"],"prefix":"10.1587","volume":"E100.D","author":[{"given":"Wenzhe","family":"ZHANG","sequence":"first","affiliation":[{"name":"Science and Technology on Parallel and Distributed Processing Laboratory, Collaborative, Innovation Center of High Performance Computing, State Key Laboratory of High-end Server & Storage Technology, College of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kai","family":"LU","sequence":"additional","affiliation":[{"name":"Science and Technology on Parallel and Distributed Processing Laboratory, Collaborative, Innovation Center of High Performance Computing, State Key Laboratory of High-end Server & Storage Technology, College of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoping","family":"WANG","sequence":"additional","affiliation":[{"name":"Science and Technology on Parallel and Distributed Processing Laboratory, Collaborative, Innovation Center of High Performance Computing, State Key Laboratory of High-end Server & Storage Technology, College of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"JIAN","sequence":"additional","affiliation":[{"name":"College of Computer, National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] S.R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz, D. Reddy, R. Sankaran, and J. Jackson, \u201cSystem software for persistent memory,\u201d Proc. Ninth European Conference on Computer Systems, pp.1-15, ACM, 2014.","DOI":"10.1145\/2592798.2592814"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] V. Singhal, S.V. Kakkad, and P.R. Wilson, \u201cTexas: An efficient, portable persistent store,\u201d Persistent Object Systems, pp.11-33, Springer, 1993.","DOI":"10.1007\/978-1-4471-3209-7_2"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Atkinson and R. Morrison, \u201cOrthogonally persistent object systems,\u201d The VLDB Journal \u2014 The International Journal on Very Large Data Bases, vol.4, no.3, pp.319-401, 1995.","DOI":"10.1007\/978-1-4471-2122-0"},{"key":"4","unstructured":"[4] L. DeMichiel and M. Keith, \u201cJava persistence API,\u201d JSR, vol.220, 2006."},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] H. Volos, A.J. Tack, and M.M. Swift, \u201cMnemosyne: Lightweight persistent memory,\u201d ACM SIGARCH Computer Architecture News, vol.39, no.1, pp.91-104, ACM, 2011.","DOI":"10.1145\/1950365.1950379"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] J. Coburn, A.M. Caulfield, A. Akel, L.M. Grupp, R.K. Gupta, R. Jhala, and S. Swanson, \u201cNv-heaps: making persistent objects fast and safe with next-generation, non-volatile memories,\u201d ACM SIGARCH Computer Architecture News, vol.39, no.1, pp.105-118, ACM, 2011.","DOI":"10.1145\/1950365.1950380"},{"key":"7","unstructured":"[7] B.G. Johnson and C.H. Dennison, \u201cPhase change memory,\u201d US Patent 6,791,102, Sept. 14 2004."},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] W. Xu, H. Sun, X. Wang, Y. Chen, and T. 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Olukotun, \u201cStamp: Stanford transactional applications for multi-processing,\u201d Workload Characterization, 2008, IISWC 2008, IEEE International Symposium on, pp.35-46, IEEE, 2008.","DOI":"10.1109\/IISWC.2008.4636089"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] J. Condit, E.B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee, \u201cBetter I\/O through byte-addressable, persistent memory,\u201d Proc. ACM SIGOPS 22nd symposium on Operating systems principles, pp.133-146, ACM, 2009.","DOI":"10.1145\/1629575.1629589"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] X. Wu and A.L.N. Reddy, \u201cSCMFS: a file system for storage class memory,\u201d Proc. 2011 International Conference for High Performance Computing, Networking, Storage and Analysis, p.39, ACM, 2011.","DOI":"10.1145\/2063384.2063436"},{"key":"22","unstructured":"[22] M.A. Olson, K. Bostic, and M.I. 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Levy, \u201cOperating system implications of fast, cheap, non-volatile memory,\u201d Proc. 13th USENIX conference on Hot topics in operating systems, p.2, USENIX Association, 2011."},{"key":"27","unstructured":"[27] E. Lee, H. Bahn, and S.H. Noh, \u201cUnioning of the buffer cache and journaling layers with non-volatile memory,\u201d FAST, pp.73-80, 2013."}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/5\/E100.D_2016EDP7429\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:15:31Z","timestamp":1750212931000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/5\/E100.D_2016EDP7429\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":27,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016edp7429","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"type":"print","value":"0916-8532"},{"type":"electronic","value":"1745-1361"}],"subject":[],"published":{"date-parts":[[2017]]}}}