{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:57:00Z","timestamp":1750309020062,"version":"3.41.0"},"reference-count":12,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/transinf.2016fop0007","type":"journal-article","created":{"date-parts":[[2017,5,31]],"date-time":"2017-05-31T22:24:02Z","timestamp":1496269442000},"page":"1182-1189","source":"Crossref","is-referenced-by-count":0,"title":["Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests"],"prefix":"10.1587","volume":"E100.D","author":[{"given":"Hiroshi","family":"IWATA","sequence":"first","affiliation":[{"name":"National Institute of Technology, Kisarazu College"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nanami","family":"KATAYAMA","sequence":"additional","affiliation":[{"name":"National Institute of Technology, Nara College"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ken'ichi","family":"YAMAGUCHI","sequence":"additional","affiliation":[{"name":"National Institute of Technology, Nara College"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] \u201cInternational technology roadmap for semiconductors 2011 edition: Design,\u201d 2011."},{"key":"2","unstructured":"[2] M. Fujita, \u201cGuide to verification techniques for system LSI \u2014 equivalence checking for logical circuits \u2014 ,\u201d Design Wave Magazine, Feb. 2004. (in Japanese)."},{"key":"3","unstructured":"[3] Y. Sato, S. Hamada, T. Maeda, A. Takatori, Y. Nozuyama, and S. Kajihara, \u201cInvisible delay quality \u2014 SDQM model lights up what could not be seen,\u201d Proc. International Test Conference, 47.1, 2005."},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] K.-T. Cheng and H.-C. Chen, \u201cClassification and identification of nonrobust untestable path delay faults,\u201d IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.15, no.8, pp.845-853, Aug. 1996.","DOI":"10.1109\/43.511566"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Kajihara, K. Kinoshita, I. Pomeranz, and S.M. Reddy, \u201cA method for identifying robust dependent and functionally unsensitizable paths,\u201d Proc. International Conference on VLSI Design, pp.82-87, Jan. 1997.","DOI":"10.1109\/ICVD.1997.567965"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] Y. Shao, S.M. Reddy, S. Kajihara, and I. Pomeranz, \u201cAn efficient method to identify untestable path delay faults,\u201d Proc. Asian Test Symposium, pp.233-238, 2001.","DOI":"10.1109\/ATS.2001.990287"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] J. Moondanos and J. Abraham, \u201cSequential redundancy identification using verification techniques,\u201d Proc. International Test Conference, pp.197-205, 1992.","DOI":"10.1109\/TEST.1992.527820"},{"key":"8","unstructured":"[8] M. Abramovici and M.A. Iyer, \u201cMethod for identifying untestable faults in logic circuits,\u201d US Patent 5,566,187, Oct. 1996."},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] D. Moundanos, J.A. Abraham, and Y.V. Hoskote, \u201cAbstraction techniques for validation coverage analysis and test generation,\u201d IEEE Trans. Comput., vol.47, no.1, pp.2-14, Jan. 1998.","DOI":"10.1109\/12.656068"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] I. Pomeranz, \u201cFast identification of undetectable transition faults under functional broadside tests,\u201d IEEE Trans. Comput., vol.61, no.6, pp.905-910, 2012.","DOI":"10.1109\/TC.2011.111"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] X. Liu and M.S. Hsiao, \u201cA novel transition fault ATPG that reduces yield loss,\u201d IEEE Des. Test. Comput., vol.22, no.6, pp.576-584, 2005.","DOI":"10.1109\/MDT.2005.126"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] F. Corno, M.S. Reorda, and G. Squillero, \u201cRt-level itc'99 benchmarks and first atpg results,\u201d IEEE Des. Test. Comput., vol.17, no.3, pp.44-53, 2000.","DOI":"10.1109\/54.867894"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/6\/E100.D_2016FOP0007\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:03:37Z","timestamp":1750284217000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/6\/E100.D_2016FOP0007\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":12,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016fop0007","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"type":"print","value":"0916-8532"},{"type":"electronic","value":"1745-1361"}],"subject":[],"published":{"date-parts":[[2017]]}}}