{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T09:43:48Z","timestamp":1774691028102,"version":"3.50.1"},"reference-count":9,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"8","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/transinf.2016lop0014","type":"journal-article","created":{"date-parts":[[2017,7,31]],"date-time":"2017-07-31T18:19:46Z","timestamp":1501525186000},"page":"1611-1617","source":"Crossref","is-referenced-by-count":6,"title":["Double-Rate Tomlinson-Harashima Precoding for Multi-Valued Data Transmission"],"prefix":"10.1587","volume":"E100.D","author":[{"given":"Yosuke","family":"IIJIMA","sequence":"first","affiliation":[{"name":"National Instutute of Technology, Oyama College"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yasushi","family":"YUMINAKA","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Gunma University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] J.F. Bulzacchelli, \u201cEqualization for Electrical Links,\u201d IEEE Solid State Circuits Mag., vol.7, no.4, pp.23-31, 2015. 10.1109\/mssc.2015.2475996","DOI":"10.1109\/MSSC.2015.2475996"},{"key":"2","unstructured":"[2] T. Kawamoto, T. Norimatsu, K. Kogo, F. Yuki, N. Nakajima, M. Tsuge, T. Usuji, T. Hokari, H. Koba, T. Komori, J. Nasu, T. Kawamata, Y. Ito, S. Umai, J. Kumazawa, H. Kurahashi, T. Muto, T. Yamashita, M. Hasegawa, and K. Higeta, \u201cMulti-Standard 185fs<i><sub>rms<\/sub><\/i> 0.3-to-28Gb\/s 40dB Backplane Signal Conditioner with Adaptive Pattern-Match 36-Tap DFE and Data-Rate-Adjustment PLL in 28nm CMOS,\u201d IEEE International Solid-State Circuit Conference, pp.54-55, 2015. 10.1109\/isscc.2015.7062922"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] Y. Iijima, Y. Takada, and Y. Yuminaka, \u201cHigh-Speed Interconnection for VLSI Systems using Multiple-Valued Signaling with Tomlinson-Harashima Precoding,\u201d IEICE Trans. on Information &amp; Systems, vol.E97-D, no.9, pp.2296-2303, 2014. 10.1587\/transinf.2013lop0021","DOI":"10.1587\/transinf.2013LOP0021"},{"key":"4","unstructured":"[4] Y.Iijima and Y.Yuminaka, \u201cEvaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding,\u201d IEEE Proc. 44th International Symp. Multiple-Valued Logic, pp.138-143, May 2014. 10.1109\/ismvl.2014.32"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] Y. Yuminaka and Y. Iijima, \u201cMultiple-Valued Signaling for High-Speed Serial Links Using Tomlinson-Harashima Precoding,\u201d IEEE J. Emerging and Selected Topics in Circuits and Systems, vol.6, no.1, pp.25-33, 2016. 10.1109\/jetcas.2016.2528738","DOI":"10.1109\/JETCAS.2016.2528738"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] M. Tomlinson, \u201cNew automatic equaliser employing modulo arithmetic,\u201d Electronics Letters, vol.7, pp.138-139, 1971. 10.1049\/el:19710089","DOI":"10.1049\/el:19710089"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] H. Harashima and H. Miyakawa, \u201cMatched-transmission technique for channels with intersymbol interference,\u201d IEEE Trans. Commun., vol.COM-20, no.4, pp.774-780, 1972. 10.1109\/tcom.1972.1091221","DOI":"10.1109\/TCOM.1972.1091221"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] M. Kossel, T. Toifl, P.A. Frances, M. Brandli, C. Menolfi, P. Buchmann, L. Kull, T.M. Andersen, and T. Morf, \u201cA 10 Gb\/s 8-Tap 6b 2-PAM\/4-PAM Tomlinson-Harashima precoding transmitter for future memorylinkapplications in 22-nm SOI CMOS,\u201d IEEE J. solid-state circuits, vol.48, no.12, pp.3268-3284, 2013. 10.1109\/jssc.2013.2279057","DOI":"10.1109\/JSSC.2013.2279057"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] B. Analui, A. Rylyakov, S. Rylov, M. Meghelli, and A. Hajimiri, \u201cA 10-Gb\/s two-dimensional eye-opening monitor in 0.13-um standard CMOS,\u201d IEEE J. Solid-State Circuits, vol.40, no.12, pp.2689-2699, 2005. 10.1109\/jssc.2005.856576","DOI":"10.1109\/JSSC.2005.856576"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/8\/E100.D_2016LOP0014\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,8,5]],"date-time":"2017-08-05T00:20:07Z","timestamp":1501892407000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/8\/E100.D_2016LOP0014\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":9,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016lop0014","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}