{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T10:20:03Z","timestamp":1649067603445},"reference-count":19,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"8","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1587\/transinf.2016lop0015","type":"journal-article","created":{"date-parts":[[2017,7,31]],"date-time":"2017-07-31T18:19:47Z","timestamp":1501525187000},"page":"1618-1624","source":"Crossref","is-referenced-by-count":0,"title":["Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme"],"prefix":"10.1587","volume":"E100.D","author":[{"given":"Daisuke","family":"SUZUKI","sequence":"first","affiliation":[{"name":"Frontier Research Institute for Interdisciplinary Sciences, Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takahiro","family":"HANYU","sequence":"additional","affiliation":[{"name":"Research Institute of Electrical Communication, Tohoku University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] F.-Li Yuan, C.C. Wang, T.-H. Yu, and D. Markovic, \u201cA multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing,\u201d IEEE J. Solid-State Circuits, vol.50, no.1, pp.137-149, Jan. 2015. 10.1109\/jssc.2014.2372034","DOI":"10.1109\/JSSC.2014.2372034"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Y.Y. Liauw, Z. Zhang, W. Kim, A.E. Gamal, and S.S. Wong, \u201cNonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory,\u201d IEEE Int. Conf. Solid-State Circuits Dig. Tech. Papers, pp.406-407, Feb. 2012. 10.1109\/isscc.2012.6177067","DOI":"10.1109\/ISSCC.2012.6177067"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Miyamura, M. Tada, T. Sakamoto, N. Banno, K. Okamoto, N. Iguchi, and H. Hada, \u201cFirst demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch,\u201d International Electron Device Meeting Tech. Dig., pp.247-250, Dec. 2012. 10.1109\/iedm.2012.6479020","DOI":"10.1109\/IEDM.2012.6479020"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] S. Yamamoto, Y. Shuto, and S. Sugahara, \u201cNonvolatile power-gating field-programmable gate array using nonvolatile static random access memory and nonvolatile flip-flops based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions,\u201d Jpn. J. Appl. Phys., vol.51, no.11S, p.11PB02, 2012. 10.7567\/jjap.51.11pb02","DOI":"10.7567\/JJAP.51.11PB02"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, \u201cSix-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series\/parallel-connected magnetic tunnel junctions,\u201d J. Appl. Phys., vol.111, no.7, 07E318, Feb. 2012. 10.1063\/1.3672411","DOI":"10.1063\/1.3672411"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, \u201cFabrication of a 3000-6-input-LUTs embedded and block-Level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure,\u201d Symp. VLSI Circuits Dig. Tech. Papers, pp.172-173, June 2015. 10.1109\/vlsic.2015.7231371","DOI":"10.1109\/VLSIC.2015.7231371"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] K. Huang, Y. Ha, R. Zhao, A. Kumar, and Y. Lian, \u201cA low active leakage and high reliability phase change memory (PCM) based non-volatile FPGA storage element,\u201d IEEE Trans. Circuits and Syst.-I, vol.61, no.9, pp.2605-2613, Dec. 2014. 10.1109\/tcsi.2014.2312499","DOI":"10.1109\/TCSI.2014.2312499"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] D. Suzuki and T. Hanyu, \u201cDesign of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure,\u201d IEEE Midwest Symp. Circuits and Systems, pp.317-320, Aug. 2015. 10.1109\/mwscas.2015.7282195","DOI":"10.1109\/MWSCAS.2015.7282195"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, \u201cCost-efficient self-terminated write driver for spin-transfer-torque RAM and logic,\u201d IEEE Trans. Magn., vol.50, no.11, pp.1-4, Nov. 2014. 10.1109\/tmag.2014.2322387","DOI":"10.1109\/TMAG.2014.2322387"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] D. Suzuki and T. Hanyu, \u201cMagnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver,\u201d J. Appl. Phys., vol.117, no.17, pp.1-3, Jan. 2015. 10.1063\/1.4906760","DOI":"10.1063\/1.4906760"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] S. Ikeda, K. Miura, H. Yamamoto, K. Mizunuma, H.D. Gan, M. Endo, S. Kanai, J. Hayakawa, F. Matsukura, and H. Ohno, \u201cAperpendicular-anisotropy CoFeB-MgO magnetic tunnel junction,\u201d Nature Materials, vol.9, no.9, pp.721-724, July 2010. 10.1038\/nmat2804","DOI":"10.1038\/nmat2804"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] C. Yoshida, T. Ochiai, Y. Iba, Y. Yamazaki, K. Tsunoda, A. Takahashi, and T. Sugii, \u201cDemonstration of non-volatile working memory through interface engineering in STT-MRAM,\u201d IEEE Symp. VLSI Technology, Dig. Tech. Papers, pp.59-60, June 2012. 10.1109\/vlsit.2012.6242460","DOI":"10.1109\/VLSIT.2012.6242460"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] H. Sato, M. Yamanouchi, S. Ikeda, S. Fukami, F. Matsukura, and H. Ohno, \u201cMgO\/CoFeB\/Ta\/CoFeB\/MgO recording structure in magnetic tunnel junctions with perpendicular easy axis,\u201d IEEE Trans. Magn., vol.49, no.7, pp.4437-4440, July 2013. 10.1109\/tmag.2013.2251326","DOI":"10.1109\/TMAG.2013.2251326"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] V. Betz, J. Rose, and A. Marquardt, \u201cArcitecture and CAD for deep-submicron FPGAs,\u201d Kluwer Academic Publishers, 1999.","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] E. Ahmed and J. Rose, \u201cThe effect of LUT and cluster size on deep-submicron FPGA performance and density,\u201d IEEE Trans. VLSI Syst., vol.12, no.3, pp.288-298, March 2004. 10.1109\/tvlsi.2004.824300","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, S. Fukami, H. Sato, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, \u201cDesign and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure,\u201d J. Appl. Phys., vol.115, no.17, pp.1-3, April 2014. 10.1063\/1.4868332","DOI":"10.1063\/1.4868332"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] P. Wang, X. Chen, Y. Chen, H. Li, S. Kang, X. Zhu, and W. Wu, \u201cA 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis,\u201d Proc. IEEE Custom Integrated Circuits Conf., pp.1-4, Sept. 2011. 10.1109\/cicc.2011.6055392","DOI":"10.1109\/CICC.2011.6055392"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] N. Sakimura, R. Nebashi, Y. Tsuji, H. Honjo, T. Sugibayashi, H. Koike, T. Ohsawa, S. Fukami, T. Hanyu, H. Ohno, and T. Endoh, \u201cHigh-speed simulator including accurate MTJ models for spintronics circuit design,\u201d Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp.1971-1974, May 2012. 10.1109\/iscas.2012.6271663","DOI":"10.1109\/ISCAS.2012.6271663"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] J. Luu, N. Ahmed, K.B. Kent, J. Anderson, J. Rose, V. Betz, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, and T. Liu, \u201cVTR 7.0: next generation architecture and CAD system for FPGAs,\u201d ACM Trans. Reconf. Tech. Syst., vol.7, no.2, pp.6:1-6:30, June 2014. 10.1145\/2617593","DOI":"10.1145\/2617593"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/8\/E100.D_2016LOP0015\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T17:37:15Z","timestamp":1569951435000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E100.D\/8\/E100.D_2016LOP0015\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":19,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2017]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016lop0015","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}