{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,12]],"date-time":"2025-06-12T23:40:03Z","timestamp":1749771603649,"version":"3.41.0"},"reference-count":23,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/transinf.2016pap0027","type":"journal-article","created":{"date-parts":[[2016,11,30]],"date-time":"2016-11-30T22:15:09Z","timestamp":1480544109000},"page":"3004-3012","source":"Crossref","is-referenced-by-count":1,"title":["GPU-Accelerated Bulk Execution of Multiple-Length Multiplication with Warp-Synchronous Programming Technique"],"prefix":"10.1587","volume":"E99.D","author":[{"given":"Takumi","family":"HONDA","sequence":"first","affiliation":[{"name":"Department of Information Engineering, Hiroshima University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yasuaki","family":"ITO","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Hiroshima University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koji","family":"NAKANO","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Hiroshima University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] T. Honda, Y. Ito, and K. Nakano, \u201cA warp-synchronous implementation for multiple-length multiplication on the GPU,\u201d Proc. International Symposium on Computing and Networking, pp.96-102, 2015.","DOI":"10.1109\/CANDAR.2015.13"},{"key":"2","unstructured":"[2] NVIDIA Corporation, \u201cCUDA ZONE.\u201d https:\/\/developer.nvidia.com\/cuda-zone"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] J. Diaz, C. Mu\u00f1oz-Caro, and A. Ni\u00f1o, \u201cA survey of parallel programming models and tools in the multi and many-core era,\u201d IEEE Trans. Parallel Distrib. Syst., vol.23, no.8, pp.1369-1386, Aug. 2012.","DOI":"10.1109\/TPDS.2011.308"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Z. Wei and J. JaJa, \u201cOptimization of linked list prefix computations on multithreaded GPUs using CUDA,\u201d Proc. International Parallel and Distributed Processing Symposium, pp.1-8, 2010.","DOI":"10.1109\/IPDPS.2010.5470455"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Y. Ito and K. Nakano, \u201cA GPU implementation of dynamic programming for the optimal polygon triangulation,\u201d IEICE Trans. Inf. & Syst., vol.E96-D, no.12, pp.2596-2603, 2013.","DOI":"10.1587\/transinf.E96.D.2596"},{"key":"6","unstructured":"[6] J. Katz and Y. Lindell, Introduction to Modern Cryptography, 2nd ed., Chapman & Hall\/CRC Cryptography and Network Security Series, CRC Press, 2014."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] L.M. Vandersypen, M. Steffen, G. Breyta, C.S. Yannoni, M.H. Sherwood, and I.L. Chuang, \u201cExperimental realization of Shor's quantum factoring algorithm using nuclear magnetic resonance,\u201d Nature, vol.414, no.6566, pp.883-887, 2001.","DOI":"10.1038\/414883a"},{"key":"8","unstructured":"[8] NVIDIA Corporation, Tuning CUDA Applications for Kepler Version 7.0, 2015."},{"key":"9","unstructured":"[9] A.L. Toom, \u201cThe complexity of a scheme of functional elements realizing the multiplication of integers,\u201d Soviet Mathematics, vol.3, pp.714-716, 1963."},{"key":"10","unstructured":"[10] T. Granlund, \u201cGNU MP: The GNU multiple precision arithmetic library,\u201d http:\/\/gmplib.org\/"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] N. Emmart and C.C. Weems, \u201cHigh precision integer multiplication with a GPU using Strassen's algorithm with multiple FFT sizes,\u201d Parallel Processing Letters, vol.21, no.3, pp.359-375, 2011.","DOI":"10.1142\/S0129626411000266"},{"key":"12","unstructured":"[12] H. Bantikyan, \u201cBig integer multiplication with CUDA FFT (cuFFT) library,\u201d Int. J. Innovative Research in Computer and Communication Engineering, vol.2, no.11, pp.6317-6325, 2014."},{"key":"13","unstructured":"[13] R.J. Fateman, \u201cWhen is FFT multiplication of arbitrary-precision polynomials practical?,\u201d Tech. Rep., University of California, Berkeley, 2006."},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] K. Zhao and X. Chu, \u201cGPUMP: A multiple-precision integer library for GPUs,\u201d Proc. 2010 IEEE 10th International Conference on Computer and Information Technology, pp.1164-1168, 2010.","DOI":"10.1109\/CIT.2010.211"},{"key":"15","unstructured":"[15] K. Kitano and N. Fujimoto, \u201cMultiple precision integer multiplication on GPUs,\u201d Proc. International Conference on Parallel and Distributed Processing Techniques and Applications, pp.236-242, 2014."},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] D. Takafuji, K. Nakano, and Y. Ito, \u201cC2CU: CUDA C program generator for bulk execution of a sequential algorithm,\u201d Proc. International Conference on Algorithms and Architectures for Parallel Processing, pp.178-191, 2014.","DOI":"10.1007\/978-3-319-11194-0_14"},{"key":"17","unstructured":"[17] NVIDIA Corporation, CUDA C Programming Guide Version 7.0, 2015."},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] D. Man, K. Uda, H. Ueyama, Y. Ito, and K. Nakano, \u201cImplementations of a parallel algorithm for computing Euclidean distance map in multicore processors and GPUs,\u201d Int. J. Networking and Computing, vol.1, no.2, pp.260-276, July 2011.","DOI":"10.15803\/ijnc.1.2_260"},{"key":"19","unstructured":"[19] NVIDIA Corporation, CUDA C Best Practice Guide Version 7.0, 2015."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] P.G. Comba, \u201cExponentiation cryptosystems on the IBM PC,\u201d IBM Systems Journal, vol.29, no.4, pp.526-538, 1990.","DOI":"10.1147\/sj.294.0526"},{"key":"21","unstructured":"[21] NVIDIA Corporation, Parallel Thread Execution ISA Version 3.2, 2013."},{"key":"22","unstructured":"[22] NVIDIA Corporation, \u201cWhitepaper NVIDIA GeForce GTX 980 v1.1,\u201d 2014."},{"key":"23","unstructured":"[23] T. Nakayama, \u201cThe CUDA multiple precision arithmetic library (CUMP) version 1.0.1.\u201d https:\/\/github.com\/skystar0227\/CUMP"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E99.D\/12\/E99.D_2016PAP0027\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,12]],"date-time":"2025-06-12T23:25:08Z","timestamp":1749770708000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E99.D\/12\/E99.D_2016PAP0027\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":23,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016pap0027","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"type":"print","value":"0916-8532"},{"type":"electronic","value":"1745-1361"}],"subject":[],"published":{"date-parts":[[2016]]}}}