{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,9]],"date-time":"2023-09-09T00:25:31Z","timestamp":1694219131700},"reference-count":23,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/transinf.2016pap0029","type":"journal-article","created":{"date-parts":[[2016,11,30]],"date-time":"2016-11-30T22:11:15Z","timestamp":1480543875000},"page":"2901-2910","source":"Crossref","is-referenced-by-count":4,"title":["An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach"],"prefix":"10.1587","volume":"E99.D","author":[{"given":"Tatsuya","family":"KAWAMOTO","sequence":"first","affiliation":[{"name":"Department of Information Engineering, Hiroshima University"}]},{"given":"Xin","family":"ZHOU","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Hiroshima University"}]},{"given":"Jacir L.","family":"BORDIM","sequence":"additional","affiliation":[{"name":"Department of Computer Science, University of Brasilia"}]},{"given":"Yasuaki","family":"ITO","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Hiroshima University"}]},{"given":"Koji","family":"NAKANO","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Hiroshima University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] T. Kawamoto, Y. Ito, and K. Nakano, \u201cA flexible-length-arithmetic processor based on FDFM approach in FPGAs,\u201d Proc. of International Symposium on Computing and Networking, pp.364-370, 2015.","DOI":"10.1109\/CANDAR.2015.12"},{"key":"2","unstructured":"[2] Xilinx Inc., Virtex-6 FPGA Configuration User Guide (v3.8), 2014."},{"key":"3","unstructured":"[3] Xilinx Inc., Virtex-6 FPGA DSP48E1 Slice User Guide (v1.3), 2011."},{"key":"4","unstructured":"[4] Xilinx Inc., Virtex-6 FPGA Memory Resources (v1.8), 2014."},{"key":"5","unstructured":"[5] G. Novak, \u201cArtificial intelligence,\u201d in Academic Press Dictionary of Science and Technology, p.160, Academic Press, San Diego, CA, 1992."},{"key":"6","unstructured":"[6] G.T. Nicol, Flex: The Lexical Scanner Generator, Free Software Foundation, 1993."},{"key":"7","unstructured":"[7] C. Donnelly and R. Stallman, Bison: The YACC-compatible Parser Generator, Free Software Foundation, 1995."},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] Y. Ago, A. Inoue, K. Nakano, and Y. Ito, \u201cThe parallel FDFM processor core approach for neural networks,\u201d Proc. of International Conference on Networking and Computing, pp.113-119, 2011.","DOI":"10.1109\/ICNC.2011.24"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] S. Bo, K. Kawakami, K. Nakano, and Y. Ito, \u201cAn RSA encryption hardware algorithm using a single DSP block and single block RAM on the FPGA,\u201d International Journal of Networking and Computing, vol.1, no.2, pp.277-289, 2011.","DOI":"10.15803\/ijnc.1.2_277"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Y. Ito, K. Nakano, and S. Bo, \u201cThe parallel FDFM processor core approach for CRT-based RSA decryption,\u201d Int. J. Networking and Computing, vol.2, pp.56-78, 2012.","DOI":"10.15803\/ijnc.2.1_79"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] M.N.I. Mondal, K. Sai, K. Nakano, and Y. Ito, \u201cA flexible-length-arithmetic processor using embedded DSP slices and block RAMs in FPGAs,\u201d Proc. of International Symposium on Computing and Networking, pp.75-84, 2013.","DOI":"10.1109\/CANDAR.2013.19"},{"key":"12","unstructured":"[12] K. Sai, A design of a flexible-length-arithmetic system using embedded DSP slices in FPGAs, Master's thesis, Hiroshima University, 2012 (in Japanese)."},{"key":"13","unstructured":"[13] A. Kalathungal, An Arbitrary Precision Integer Arithmetic Library for FPGA s, Ph.D. Thesis, University of Cincinnati, 2013."},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] O.A. Pf\u00e4nder, R. Nopper, H.-J. Pfleiderer, S. Zhou, and A. Bermak, \u201cConfigurable blocks for multi-precision multiplication,\u201d IEEE International Symposium on Electronic Design, Test and Applications, pp.478-481, 2008.","DOI":"10.1109\/DELTA.2008.109"},{"key":"15","unstructured":"[15] C.E. LaForest, High-Speed Soft-Processor Architecture for FPGA Overlays, Ph.D. Thesis, University of Toronto, 2015."},{"key":"16","unstructured":"[16] S. McGettrick, K. Patel, and C. Bleakley, \u201cHigh performance programmable FPGA overlay for digital signal processing,\u201d in Reconfigurable Computing: Architectures, Tools and Applications, vol.6578, pp.375-384, Springer, 2011."},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] P.G. Comba, \u201cExponentiation cryptosystems on the IBM PC,\u201d IBM Systems Journal, vol.29, no.4, pp.526-538, 1990.","DOI":"10.1147\/sj.294.0526"},{"key":"18","unstructured":"[18] J.L. Hennessy and D.A. Patterson, Computer Architecture, Fourth Edition: A Quantitative Approach, Morgan Kaufmann Publishers, 2006."},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] R.L. Rivest, A. Shamir, and L.M. Adleman, \u201cA method for obtaining digital signatures and public-key cryptosystems,\u201d Commun. ACM, vol.21, no.2, pp.120-126, 1978.","DOI":"10.1145\/359340.359342"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] P.L. Montgomery, \u201cModular multiplication without trial division,\u201d Math. of Comput., vol.44, no.170, pp.519-521, 1985.","DOI":"10.1090\/S0025-5718-1985-0777282-X"},{"key":"21","unstructured":"[21] E.C. Villar and J.C. Villar, \u201cHigh performance RSA 512 bit IPCore.\u201d http:\/\/opencores.org\/project,rsa_512, 2012."},{"key":"22","unstructured":"[22] \u201cOpenCores.\u201d http:\/\/opencores.org\/"},{"key":"23","unstructured":"[23] T. Granlund, \u201cGNU MP: The GNU Multiple Precision arithmetic library.\u201d http:\/\/gmplib.org\/"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E99.D\/12\/E99.D_2016PAP0029\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T04:54:37Z","timestamp":1498366477000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E99.D\/12\/E99.D_2016PAP0029\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":23,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016pap0029","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}