{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T08:12:15Z","timestamp":1648973535234},"reference-count":19,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/transinf.2016pap0033","type":"journal-article","created":{"date-parts":[[2016,11,30]],"date-time":"2016-11-30T22:11:58Z","timestamp":1480543918000},"page":"2871-2880","source":"Crossref","is-referenced-by-count":1,"title":["Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface"],"prefix":"10.1587","volume":"E99.D","author":[{"given":"Hiroshi","family":"NAKAHARA","sequence":"first","affiliation":[{"name":"Dept. of ICS, Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomoya","family":"OZAKI","sequence":"additional","affiliation":[{"name":"Dept. of ICS, Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroki","family":"MATSUTANI","sequence":"additional","affiliation":[{"name":"Dept. of ICS, Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michihiro","family":"KOIBUCHI","sequence":"additional","affiliation":[{"name":"National Institute of Informatics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"AMANO","sequence":"additional","affiliation":[{"name":"Dept. of ICS, Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner, and P. Wyatt, \u201cThree-dimensional integrated circuits for low-power, high-bandwidth systems on a chip,\u201d Proceedings of the IEEE International Solid-State Circuits Conference, pp.268-269, Feb. 2001.","DOI":"10.1109\/ISSCC.2001.912632"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H. Amano, \u201cCastle of Chips: A New Chip Stacking Structure with Wireless Inductive Coupling for Large Scale 3-D Multicore Systems,\u201d Proceedings of 15th International Conference on Network-Based Information Systems, pp.820-825, 2012.","DOI":"10.1109\/NBiS.2012.82"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] H. Nakahara, T. Ozaki, H. Matsutani, M. Koibuchi, and H. Amano, \u201cExpandable chip stacking method for many-core architectures consisting of tiny chips,\u201d 2015 IEEE 9th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC), pp.41-48, 2015.","DOI":"10.1109\/MCSoC.2015.26"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y. Take, H. Matsutani, D. Sasaki, M. Koibuch, T. Kuroda, and H. Amano, \u201c3D NoC with Inductive-Coupling Links for Building-Block SiPs,\u201d IEEE Trans. Comput., vol.63, no.3, pp.748-763, March 2014.","DOI":"10.1109\/TC.2012.249"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, I. Nonomura, M. Saen, S. Komatsu, K. Osada, N. Irie, T. Hattori, A. Hasegawa, and T. Kuroda, \u201cAn inductive-coupling link for 3d integration of a 90nm cmos processor and a 65nm cmos sram,\u201d Proceedings of the IEEE International Solid-State Circuits Conference, pp.480-481,481a, Feb. 2009.","DOI":"10.1109\/ISSCC.2009.4977517"},{"key":"6","unstructured":"[6] Y. Kohama, Y. Sugimori, S. Saito, Y. Hasegawa, T. Sano, K. Kasuga, Y. Yoshida, K. Niitsu, N. Miura, H. Amano, and T. Kuroda, \u201cA scalable 3D processor by homogeneous chip stacking with inductive-coupling link,\u201d Proceedings of the VLSI Circuits Symposium, pp.94-95, June 2009."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] N. Miura, Y. Koizumi, Y. Take, H. Matsutani, T. Kuroda, H. Amano, R. Sakamoto, M. Namiki, K. Usami, M. Kondo, and H. Nakamura, \u201cA Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface,\u201d IEEE Micro, vol.33, no.6, pp.6-15, 2013.","DOI":"10.1109\/MM.2013.112"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, \u201cA 0.14pJ\/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping,\u201d Proceedings of the International Solid-State Circuits Conference (ISSCC&apos;07), pp.358-359, Feb. 2007.","DOI":"10.1109\/ISSCC.2007.373442"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] D.U. Lee, K.W. Kim, K.W. Kim, K.S. Lee, S.J. Byeon, J.H. Kim, J.H. Cho, J. Lee, and J.H. Chun, \u201cA 1.2 v 8 gb 8-channel 128 gb\/s high-bandwidth memory (hbm) stacked dram with effective i\/o test circuits,\u201d IEEE J. Solid-State Circuits, vol.50, no.1, pp.191-203, Jan. 2015.","DOI":"10.1109\/JSSC.2014.2360379"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] M. Saito, Y. Yoshida, N. Miura, H. Ishikuro, and T. Kuroda, \u201c47% power reduction and 91% area reduction in inductive-coupling programmable bus for nand flash memory stacking,\u201d Proc. IEEE Trans. Circuits Syst., vol.57, no.9, pp.2269-2278, Sept. 2010.","DOI":"10.1109\/TCSI.2010.2071670"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] P.P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, \u201cPerformance evaluation and design trade-offs for network-on-chip interconnect architectures,\u201d IEEE Trans. Comput., vol.54, no.8, pp.1025-1040, Aug. 2005.","DOI":"10.1109\/TC.2005.134"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Nguyen, J. Pezarts, G. Pratt, and S. Ward, \u201cThree-Dimensional Network Topologies,\u201d Parallel Computer and Communication (K.Bolding and L. Synder, eds), vol.853, pp.101-115, 1994.","DOI":"10.1007\/3-540-58429-3_31"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] W.S. Lacy, J.L. Cruz-Rivera, and D.S. Wills, \u201cThe Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics,\u201d IEEE Trans. Parallel Distrib. Syst., vol.9, no.9, pp.893-908, 1998.","DOI":"10.1109\/71.722222"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] C.J. Glass and L.M. Ni, \u201cThe Turn Model for Adaptive Routing,\u201d Proceedings of 19th International Symposium on Computer Architecture, pp.278-287, 1992.","DOI":"10.1109\/ISCA.1992.753324"},{"key":"15","unstructured":"[15] W.J. Dally and B.P. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004."},{"key":"16","unstructured":"[16] H. Jin, M. Frumkin, and J. Yan, \u201cThe OpenMP Implementation of NAS Parallel Benchmarks and Its Performane,\u201d NAS Technical Report NAS-99-011, Oct. 1999."},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] N. Binkert, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, D.A. Wood, B. Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, and T. Krishna, \u201cThe gem5 Simulator,\u201d ACM SIGARCH Computer Architecture News, vol.39, no.2, pp.1-7, May 2011.","DOI":"10.1145\/2024716.2024718"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] S.R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, \u201cAn 80-tile sub-100-w teraflops processor in 65-nm cmos,\u201d IEEE Jounal of Solid-State Circuits, vol.43, no.1, pp.29-41, Jan. 2008.","DOI":"10.1109\/JSSC.2007.910957"},{"key":"19","unstructured":"[19] J.L. Hennessy and D.A. Patterson, Computer Architecture, Fifth Edition: A Quantitative Approach, Morgan Kaufmann, 2011."}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E99.D\/12\/E99.D_2016PAP0033\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T04:54:37Z","timestamp":1498366477000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E99.D\/12\/E99.D_2016PAP0033\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":19,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016pap0033","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}