{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T13:10:08Z","timestamp":1649164208838},"reference-count":35,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"9","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2018,9,1]]},"DOI":"10.1587\/transinf.2017edp7296","type":"journal-article","created":{"date-parts":[[2018,8,31]],"date-time":"2018-08-31T18:43:14Z","timestamp":1535740994000},"page":"2247-2257","source":"Crossref","is-referenced-by-count":1,"title":["Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs"],"prefix":"10.1587","volume":"E101.D","author":[{"given":"Satoshi","family":"IMAMURA","sequence":"first","affiliation":[{"name":"Fujitsu Laboratories Ltd."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuichiro","family":"YASUI","sequence":"additional","affiliation":[{"name":"Institute of Mathematics for Industry, Kyushu University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koji","family":"INOUE","sequence":"additional","affiliation":[{"name":"Faculty of Information Science and Electrical Engineering, Kyushu University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takatsugu","family":"ONO","sequence":"additional","affiliation":[{"name":"Faculty of Information Science and Electrical Engineering, Kyushu University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroshi","family":"SASAKI","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Katsuki","family":"FUJISAWA","sequence":"additional","affiliation":[{"name":"Institute of Mathematics for Industry, Kyushu University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] Intel, \u201cIntel<sup>\u00ae<\/sup> Xeon<sup>\u00ae<\/sup> Processor E7-8890 v4.\u201d https:\/\/ark.intel.com\/products\/93790\/Intel-Xeon-Processor-E7-8890-v4-60M-Cache-2_20-GHz. Last accessed: March 5, 2018."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K. Kumar, K. Doshi, M. Dimitrov, and Y.-H. Lu, \u201cMemory Energy Management for an Enterprise Decision Support System,\u201d ISLPED &apos;11, pp.277-282, 2011. 10.1109\/islped.2011.5993649","DOI":"10.1109\/ISLPED.2011.5993649"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Z. Zhang, Z. Zhu, and X. Zhang, \u201cA Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality,\u201d MICRO-33, pp.32-41, 2000. 10.1145\/360128.360134","DOI":"10.1145\/360128.360134"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] D. Kaseridis, J. Stuecheli, and L.K. John, \u201cMinimalist Open-page: A DRAM Page-mode Scheduling Policy for the Many-core Era,\u201d MICRO-44, pp.24-35, 2011. 10.1145\/2155620.2155624","DOI":"10.1145\/2155620.2155624"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Rixner, W.J. Dally, U.J. Kapasi, P. Mattson, and J.D. Owens, \u201cMemory Access Scheduling,\u201d ISCA &apos;00, pp.128-138, 2000. 10.1145\/339647.339668","DOI":"10.1145\/339647.339668"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] O. Mutlu and T. Moscibroda, \u201cStall-Time Fair Memory Access Scheduling for Chip Multiprocessors,\u201d MICRO-40, pp.146-160, 2007. 10.1109\/micro.2007.4408252","DOI":"10.1109\/MICRO.2007.4408252"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Y. Kim, M. Papamichael, O. Mutlu, and M. Harchol-Balter, \u201cThread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior,\u201d MICRO-43, pp.65-76, 2010. 10.1109\/micro.2010.51","DOI":"10.1109\/MICRO.2010.51"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] S.P. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, and T. Moscibroda, \u201cReducing Memory Interference in Multicore Systems via Application-aware Memory Channel Partitioning,\u201d MICRO-44, pp.374-385, 2011. 10.1145\/2155620.2155664","DOI":"10.1145\/2155620.2155664"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] L. Liu, Z. Cui, M. Xing, Y. Bao, M. Chen, and C. Wu, \u201cA Software Memory Partition Approach for Eliminating Bank-level Interference in Multicore Systems,\u201d PACT &apos;12, pp.367-376, 2012. 10.1145\/2370816.2370869","DOI":"10.1145\/2370816.2370869"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] M.K. Jeong, D.H. Yoon, D. Sunwoo, M. Sullivan, I. Lee, and M. Erez, \u201cBalancing DRAM locality and parallelism in shared memory CMP systems,\u201d HPCA &apos;12, pp.1-12, 2012. 10.1109\/hpca.2012.6168944","DOI":"10.1109\/HPCA.2012.6168944"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] M. Xie, D. Tong, K. Huang, and X. Cheng, \u201cImproving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning,\u201d HPCA &apos;14, pp.344-355, 2014. 10.1109\/hpca.2014.6835945","DOI":"10.1109\/HPCA.2014.6835945"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] H. Park, S. Baek, J. Choi, D. Lee, and S.H. Noh, \u201cRegularities Considered Harmful: Forcing Randomness to Memory Accesses to Reduce Row Buffer Conflicts for Multi-core, Multi-bank Systems,\u201d ASPLOS &apos;13, pp.181-192, 2013. 10.1145\/2451116.2451137","DOI":"10.1145\/2451116.2451137"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] X. Tang, M. Kandemir, P. Yedlapalli, and J. Kotra, \u201cImproving Bank-Level Parallelism for Irregular Applications,\u201d MICRO-49, pp.1-12, 2016. 10.1109\/micro.2016.7783760","DOI":"10.1109\/MICRO.2016.7783760"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] B. Akin, F. Franchetti, and J.C. Hoe, \u201cUnderstanding the Design Space of DRAM-Optimized Hardware FFT Accelerators,\u201d ASAP &apos;14, pp.248-255, 2014. 10.1109\/asap.2014.6868669","DOI":"10.1109\/ASAP.2014.6868669"},{"key":"15","unstructured":"[15] O. Mutlu, \u201cComputer Architecture: Main Memory (Alternate Version).\u201d http:\/\/slideplayer.com\/slide\/4744474\/. Last accessed on March 5, 2018."},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] S. Imamura, Y. Yasui, K. Inoue, T. Ono, H. Sasaki, and K.Fujisawa, \u201cPower-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping,\u201d HPGDMP &apos;16, pp.17-24, 2016. 10.1109\/hpgdmp.2016.010","DOI":"10.1109\/HPGDMP.2016.010"},{"key":"17","unstructured":"[17] AMD, \u201cBIOS and Kernel Developer&apos;s Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors,\u201d 2013. Rev 3.14."},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] K. Sudan, N. Chatterjee, D. Nellans, M. Awasthi, R.Balasubramonian, and A. Davis, \u201cMicro-pages: Increasing DRAM Efficiency with Locality-Aware Data Placement,\u201d ASPLOS &apos;10, pp.219-230, 2010.","DOI":"10.1145\/1736020.1736045"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] D. Kang, H. Park, and J. Choi, \u201cEffect of Page Frame Allocation Pattern on Bank Conflicts in Multi-core Systems,\u201d RACS &apos;13, pp.467-472, 2013. 10.1145\/2513228.2513306","DOI":"10.1145\/2513228.2513306"},{"key":"20","unstructured":"[20] P. Pessl, D. Gruss, C. Maurice, M. Schwarz, and S. Mangard, \u201cDRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks,\u201d USENIX Security &apos;16, pp.565-581, 2016."},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] M. Jung, D.M. Mathew, C. Weis, N. Wehn, I. Heinrich, M.V.Natale, and S.O. Krumke, \u201cConGen: An Application Specific DRAM Memory Controller Generator,\u201d MEMSYS &apos;16, pp.257-267, 2016. 10.1145\/2989081.2989131","DOI":"10.1145\/2989081.2989131"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] A. Patel, F. Afram, S. Chen, and K. Ghose, \u201cMARSS: A Full System Simulator for Multicore x86 CPUs,\u201d DAC &apos;11, pp.1050-1055, 2011. 10.1145\/2024724.2024954","DOI":"10.1145\/2024724.2024954"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] P. Rosenfeld, E. Cooper-Balis, and B. Jacob, \u201cDRAMSim2: A Cycle Accurate Memory System Simulator,\u201d Computer Architecture Letters, vol.10, no.1, pp.16-19, Jan. 2011. 10.1109\/l-ca.2011.4","DOI":"10.1109\/L-CA.2011.4"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] G.E. Blelloch, J.T. Fineman, P.B. Gibbons, and J. Shun, \u201cInternally Deterministic Parallel Algorithms Can Be Fast,\u201d PPoPP &apos;12, pp.181-192, 2012. 10.1145\/2145816.2145840","DOI":"10.1145\/2145816.2145840"},{"key":"25","unstructured":"[25] R.C. Murphy, K.B. Wheeler, B.W. Barrett, and J.A. Ang, Introducing the Graph 500. Cray User&apos;s Group (CUG), 2010."},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] Y. Yasui, K. Fujisawa, E.L. Goh, J. Baron, A. Sugiura, and T. Uchiyama, \u201cNUMA-aware Scalable Graph Traversal on SGI UV Systems,\u201d HPGP &apos;16, pp.19-26, 2016. 10.1145\/2915516.2915522","DOI":"10.1145\/2915516.2915522"},{"key":"27","unstructured":"[27] Micron Technology, Inc., Calculating Memory System Power for DDR3, 2007."},{"key":"28","unstructured":"[28] Intel, \u201cIntel Xeon Processor E5 and E7 v3 Family Uncore Performance Monitoring Reference Manual,\u201d June 2015."},{"key":"29","unstructured":"[29] Micron, \u201cDDR4-Advantages of Migrating from DDR3.\u201d https:\/\/www.micron.com\/products\/dram\/ddr3-to-ddr4. Last accessed on March 7, 2018."},{"key":"30","unstructured":"[30] Micron, \u201cDRAM Memory In High-Speed Digital Designs.\u201d https:\/\/www.keysight.com\/upload\/cmc_upload\/All\/5Micron.pdf. Last accessed on March 1, 2018."},{"key":"31","unstructured":"[31] C. Stephan, \u201cQuantifying the Power Savings by Upgrading to DDR4 Memory on Lenovo Servers,\u201d LENOVO PRESS, 2016."},{"key":"32","unstructured":"[32] Micron, \u201c2Gb: x4, x8, x16 DDR3 SDRAM features,\u201d 2006."},{"key":"33","unstructured":"[33] Micron, \u201c4Gb: x4, x8, x16 DDR4 SDRAM features,\u201d 2014."},{"key":"34","doi-asserted-by":"crossref","unstructured":"[34] H. David, E. Gorbatov, U.R. Hanebutte, R. Khanaa, and C. Le, \u201cRAPL: Memory Power Estimation and Capping,\u201d ISLPED &apos;10, pp.189-194, 2010. 10.1145\/1840845.1840883","DOI":"10.1145\/1840845.1840883"},{"key":"35","doi-asserted-by":"crossref","unstructured":"[35] J. Treibig, G. Hager, and G. Wellein, \u201cLIKWID: A Lightweight Performance-Oriented Tool Suite for x86 Multicore Environments,\u201d ICPPW &apos;10, pp.207-216, 2010. 10.1109\/icppw.2010.38","DOI":"10.1109\/ICPPW.2010.38"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E101.D\/9\/E101.D_2017EDP7296\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,23]],"date-time":"2019-10-23T06:08:47Z","timestamp":1571810927000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E101.D\/9\/E101.D_2017EDP7296\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9,1]]},"references-count":35,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2018]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2017edp7296","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,9,1]]}}}