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Tsutsumi, \u201cFully-Functional FPGA Prototyple with Fine-Grain Programmable Body Biasing,\u201d Proc. 21st ACM\/SIGDA International Symposium on FPGA, pp.73-80, Feb. 2013. 10.1145\/2435264.2435280","DOI":"10.1145\/2435264.2435280"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[11] B. Zhai, R.G. Dreslinski, D. Blaauw, T. Mudge, and D. Sylvester, \u201cEnergy Efficient Near-threshold Chip Multi-processing,\u201d Proceedings of International Symposium on Low Power Electronics and Design, pp.32-37, Aug. 2007. 10.1145\/1283780.1283789","DOI":"10.1145\/1283780.1283789"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[12] D. Fick, R.G. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw, \u201cCentip3De: A3930DMIPS\/W Configurable Near-Threshold 3D Stacked System with 64 ARM Cortex-M3 Cores,\u201d Proceedings of International Solid-State Circuits Conference, pp.190-192, Aug. 2012. 10.1109\/isscc.2012.6176970","DOI":"10.1109\/ISSCC.2012.6176970"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[13] S. Nakamura, J. Kawasaki, Y. Kumagai, and K. Usami, \u201cMeasurement of the Minimum Energy Point in Silicon on Thin-BOX (SOTB) and Bulk MOSFET,\u201d Proc. EUROSOI-ULIS, pp.193-196, Jan. 2015. 10.1109\/ulis.2015.7063746","DOI":"10.1109\/ULIS.2015.7063746"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[14] J.T. Kao, M. Miyazaki, and A.R. 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