{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,17]],"date-time":"2023-01-17T22:12:56Z","timestamp":1673993576858},"reference-count":58,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2018,12,1]]},"DOI":"10.1587\/transinf.2018pap0003","type":"journal-article","created":{"date-parts":[[2018,11,30]],"date-time":"2018-11-30T17:27:32Z","timestamp":1543598852000},"page":"2864-2877","source":"Crossref","is-referenced-by-count":2,"title":["Parallel Precomputation with Input Value Prediction for Model Predictive Control Systems"],"prefix":"10.1587","volume":"E101.D","author":[{"given":"Satoshi","family":"KAWAKAMI","sequence":"first","affiliation":[{"name":"Graduate School of Information Science and Electrical Engineering, Kyushu University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takatsugu","family":"ONO","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Electrical Engineering, Kyushu University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshiyuki","family":"OHTSUKA","sequence":"additional","affiliation":[{"name":"Graduate School of Informatics, Kyoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koji","family":"INOUE","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Electrical Engineering, Kyushu University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] Y. Wang and S. Boyd, \u201cFast model predictive control using online optimization,\u201d IEEE Trans. Control Syst. Technol., vol.18, no.2, pp.267-278, March 2010. 10.1109\/tcst.2009.2017934","DOI":"10.1109\/TCST.2009.2017934"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H. Xu, J. Tanabe, H. Usui, S. Hosoda, T. Sano, K. Yamamoto, T. Kodaka, N. Nonogaki, N. Ozaki, and T. Miyamori, \u201cA low power many-core soc with two 32-core clusters connected by tree based noc for multimedia applications,\u201d Proc. 2012 Symposium on VLSI Circuits, pp.150-151, 2012. 10.1109\/vlsic.2012.6243834","DOI":"10.1109\/VLSIC.2012.6243834"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, \u201cTile64-processor: A 64-core soc with mesh interconnect,\u201d Proc. IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.88-598, 2008. 10.1109\/isscc.2008.4523070","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"4","unstructured":"[4] J.B. Rawlings and D.Q. Mayne, Model predictive control: theory and design, Nob Hill Publishing, 2009."},{"key":"5","unstructured":"[5] J.M. Maciejowski, Predictive control: with constraints, Pearson education, 2002."},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] A. Jadbabaie, J. Yu, and J. Hauser, \u201cUnconstrained receding-horizon control of nonlinear systems,\u201d IEEE Trans. Autom. Control, vol.46, no.5, pp.776-783, 2001. 10.1109\/9.920800","DOI":"10.1109\/9.920800"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] H. Seguchi and T. Ohtsuka, \u201cNonlinear receding horizon control of an underactuated hovercraft,\u201d International journal of robust and nonlinear control, vol.13, no.3-4, pp.381-398, 2003. 10.1002\/rnc.824","DOI":"10.1002\/rnc.824"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] H.J. Ferreau, G. Lorini, and M. Diehl, \u201cFast nonlinear model predictive control of gasoline engines,\u201d Proc. 2006 IEEE International Conference on Control Applications, pp.2754-2759, 2006. 10.1109\/cca.2006.286005","DOI":"10.1109\/CCA.2006.286005"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] T. Ohtsuka, \u201cA continuation\/gmres method for fast computation of nonlinear receding horizon control,\u201d Automatica, vol.40, no.4, pp.563-574, 2004. 10.1016\/j.automatica.2003.11.005","DOI":"10.1016\/j.automatica.2003.11.005"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[10] T. Ohtsuka and A. Kodama, \u201cAutomatic code generation system for nonlinear receding horizon control,\u201d Transactions of the Society of Instrument and Control Engineers, vol.38, no.7, pp.617-623, 2002. 10.9746\/sicetr1965.38.617","DOI":"10.9746\/sicetr1965.38.617"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] A. Bartolini, M. Cacciari, A. Tilli, and L. Benini, \u201cThermal and energy management of high-performance multicores: Distributed and self-calibrating model-predictive controller,\u201d IEEE Trans. Parallel Distrib. Syst., vol.24, no.1, pp.170-183, Jan. 2013. 10.1109\/tpds.2012.117","DOI":"10.1109\/TPDS.2012.117"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] S. Kawakami, A. Iwanaga, and K. Inoue, \u201cMany-core acceleration for model predictive control systems,\u201d Proc. First International Workshop on Many-core Embedded Systems, MES '13, New York, NY, USA, pp.17-24, ACM, 2013. 10.1145\/2489068.2489071","DOI":"10.1145\/2489068.2489071"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] S. Longo, E.C. Kerrigan, K.V. Ling, and G.A. Constantinides, \u201cParallel move blocking model predictive control,\u201d Proc. 50th IEEE Conference on Decision and Control and European Control Conference, pp.1239-1244, 2011. 10.1109\/cdc.2011.6160429","DOI":"10.1109\/CDC.2011.6160429"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] D. Soudbakhsh and A.M. Annaswamy, \u201cParallelized model predictive control,\u201d Proc. 2013 American Control Conference, pp.1715-1720, 2013. 10.1109\/acc.2013.6580083","DOI":"10.1109\/ACC.2013.6580083"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] J.L. Lions, Y. Maday, and G. Turinici, \u201cA \u201cparareal\u201d in time discretization of pde's,\u201d Comptes Rendus de l'Acad\u00e9mie des Sciences-Series I-Mathematics, vol.332, no.7, pp.661-668, 2001.","DOI":"10.1016\/S0764-4442(00)01793-6"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] L. Baffico, S. Bernard, Y. Maday, G. Turinici, and G. Z\u00e9rah, \u201cParallel-in-time molecular-dynamics simulations,\u201d Physical review E, Statistical, nonlinear, and soft matter physics, vol.66, p.057701, 12 2002. 10.1103\/physreve.66.057701","DOI":"10.1103\/PhysRevE.66.057701"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Y. Maday and G. Turinici, \u201cA parallel in time approach for quantum control: the parareal algorithm,\u201d Proc. 41st IEEE Conference on Decision and Control, vol.1, pp.62-66, Dec. 2002. 10.1109\/cdc.2002.1184468","DOI":"10.1109\/CDC.2002.1184468"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] D. Ruprecht and R. Krause, \u201cExplicit parallel-in-time integration of a linear acoustic-advection system,\u201d Computers & Fluids, vol.59, pp.72-83, 2012. 10.1016\/j.compfluid.2012.02.015","DOI":"10.1016\/j.compfluid.2012.02.015"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] D. Samaddar, D.E. Newman, and R. S\u00e1nchez, \u201cParallelization in time of numerical simulations of fully-developed plasma turbulence using the parareal algorithm,\u201d Journal of Computational Physics, vol.229, no.18, pp.6558-6573, 2010. 10.1016\/j.jcp.2010.05.012","DOI":"10.1016\/j.jcp.2010.05.012"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] E. Aubanel, \u201cScheduling of tasks in the parareal algorithm,\u201d Parallel Computing, vol.37, no.3, pp.172-182, 2011. 10.1016\/j.parco.2010.10.004","DOI":"10.1016\/j.parco.2010.10.004"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] W.R. Elwasif, S.S. Foley, D.E. Bernholdt, L.A. Berry, D. Samaddar, D.E. Newman, and R. Sanchez, \u201cA dependency-driven formulation of parareal: Parallel-in-time solution of pdes as a many-task application,\u201d Proc. 2011 ACM International Workshop on Many Task Computing on Grids and Supercomputers, MTAGS '11, New York, NY, USA, pp.15-24, ACM, 2011. 10.1145\/2132876.2132883","DOI":"10.1145\/2132876.2132883"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] R. Speck, D. Ruprecht, R. Krause, M. Emmett, M. Minion, M. Winkel, and P. Gibbon, \u201cA massively space-time parallel n-body solver,\u201d Proc. International Conference on High Performance Computing, Networking, Storage and Analysis, SC '12, Los Alamitos, CA, USA, pp.92:1-92:11, IEEE Computer Society Press, 2012.","DOI":"10.1109\/SC.2012.6"},{"key":"23","unstructured":"[23] R. Speck, D. Ruprecht, M. Emmett, M. Bolten, and R. Krause, \u201cA space-time parallel solver for the three-dimensional heat equation,\u201d Parallel Computing: Accelerating Computational Science and Engineering (CSE), vol.25, pp.263-272, 2014."},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] P.D. Vouzis, L.G. Bleris, M.G. Arnold, and M.V. Kothare, \u201cA system-on-a-chip implementation for embedded real-time model predictive control,\u201d IEEE Trans. Control Syst. Technol., vol.17, no.5, pp.1006-1017, Sept. 2009. 10.1109\/tcst.2008.2004503","DOI":"10.1109\/TCST.2008.2004503"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] A.G. Wills, G. Knagge, and B. Ninness, \u201cFast linear model predictive control via custom integrated circuit architecture,\u201d IEEE Trans. Control Syst. Technol., vol.20, no.1, pp.59-71, Jan. 2012. 10.1109\/tcst.2010.2096224","DOI":"10.1109\/TCST.2010.2096224"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] K.V. Ling, S.P. Yue, and J.M. Maciejowski, \u201cA fpga implementation of model predictive control,\u201d Proc. 2006 American Control Conference, pp.1930-1935, 2006.","DOI":"10.1109\/ACC.2006.1656502"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] J.L. Jerez, G.A. Constantinides, and E.C. Kerrigan, \u201cAn fpga implementation of a sparse quadratic programming solver for constrained predictive control,\u201d Proc. 19th ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, pp.209-218, 2011. 10.1145\/1950413.1950454","DOI":"10.1145\/1950413.1950454"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] J.L. Jerez, G.A. Constantinides, and E.C. Kerrigan, \u201cFpga implementation of an interior point solver for linear model predictive control,\u201d Proc. 2010 International Conference on Field-Programmable Technology, pp.316-319, 2010. 10.1109\/fpt.2010.5681439","DOI":"10.1109\/FPT.2010.5681439"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] L. Hammond, M. Willey, and K. Olukotun, \u201cData speculation support for a chip multiprocessor,\u201d Proc. Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, pp.58-69, 1998. 10.1145\/291069.291020","DOI":"10.1145\/291069.291020"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] M.K. Prabhu and K. Olukotun, \u201cExposing speculative thread parallelism in spec2000,\u201d Proc. Tenth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp.142-152, 2005. 10.1145\/1065944.1065964","DOI":"10.1145\/1065944.1065964"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] N. Vachharajani, R. Rangan, E. Raman, M.J. Bridges, G. Ottoni, and D.I. August, \u201cSpeculative decoupled software pipelining,\u201d Proc. 16th International Conference on Parallel Architecture and Compilation Techniques, pp.49-59, 2007.","DOI":"10.1109\/PACT.2007.4336199"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] M. Gupta and R. Nim, \u201cTechniques for speculative run-time parallelization of loops,\u201d Proc. IEEE\/ACM Conference on Supercomputing, p.12, 1998. 10.1109\/sc.1998.10053","DOI":"10.1109\/SC.1998.10053"},{"key":"33","doi-asserted-by":"crossref","unstructured":"[33] M. Cintra and D.R. Llanos, \u201cToward efficient and robust software speculative parallelization on multiprocessors,\u201d Proc. Ninth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp.13-24, 2003. 10.1145\/781499.781501","DOI":"10.1145\/781499.781501"},{"key":"34","doi-asserted-by":"crossref","unstructured":"[34] I. Park, B. Falsafi, and T.N. Vijaykumar, \u201cImplicitly-multithreaded processors,\u201d Proc. 30th Annual International Symposium on Computer Architecture, pp.39-51, 2003. 10.1109\/isca.2003.1206987","DOI":"10.1109\/ISCA.2003.1206987"},{"key":"35","doi-asserted-by":"publisher","unstructured":"[35] J.G. Steffan, C. Colohan, A. Zhai, and T.C. Mowry, \u201cThe stampede approach to thread-level speculation,\u201d ACM Transactions on Computer Systems, vol.23, no.3, pp.253-300, Aug. 2005. 10.1145\/1082469.1082471","DOI":"10.1145\/1082469.1082471"},{"key":"36","doi-asserted-by":"crossref","unstructured":"[36] P. Marcuello, A. Gonz\u00e1lez, and J. Tubella, \u201cSpeculative multithreaded processors,\u201d Proc. 12th International Conference on Supercomputing, pp.77-84, 1998. 10.1145\/277830.277850","DOI":"10.1145\/277830.277850"},{"key":"37","doi-asserted-by":"crossref","unstructured":"[37] E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith, \u201cTrace processors,\u201d Proc. 30th Annual ACM\/IEEE International Symposium on Microarchitecture, pp.138-148, 1997. 10.1109\/micro.1997.645805","DOI":"10.1109\/MICRO.1997.645805"},{"key":"38","doi-asserted-by":"crossref","unstructured":"[38] A. Roth and G.S. Sohi, \u201cSpeculative data-driven multithreading,\u201d Proc. Seventh International Symposium on High-Performance Computer Architecture, pp.37-48, 2001. 10.1109\/hpca.2001.903250","DOI":"10.1109\/HPCA.2001.903250"},{"key":"39","doi-asserted-by":"crossref","unstructured":"[39] Y. Sazeides and J.E. Smith, \u201cThe predictability of data values,\u201d Proc. 30th Annual ACM\/IEEE International Symposium on Microarchitecture, pp.248-258, 1997. 10.1109\/micro.1997.645815","DOI":"10.1109\/MICRO.1997.645815"},{"key":"40","doi-asserted-by":"crossref","unstructured":"[40] P. Marcuello, J. Tubella, and A. Gonz\u00e1lez, \u201cValue prediction for speculative multithreaded architectures,\u201d Proc. 32nd Annual ACM\/IEEE International Symposium on Microarchitecture, pp.230-236, 1999. 10.1109\/micro.1999.809461","DOI":"10.1109\/MICRO.1999.809461"},{"key":"41","doi-asserted-by":"crossref","unstructured":"[41] Y. Sazeides, S. Vassiliadis, and J.E. Smith, \u201cThe performance potential of data dependence speculation & collapsing,\u201d Proc. 29th Annual ACM\/IEEE International Symposium on Microarchitecture, pp.238-247, 1996. 10.1109\/micro.1996.566465","DOI":"10.1109\/MICRO.1996.566465"},{"key":"42","doi-asserted-by":"crossref","unstructured":"[42] B. Calder, G. Reinman, and D.M. Tullsen, \u201cSelective value prediction,\u201d Proc. 26th Annual International Symposium on Computer Architecture, pp.64-74, 1999. 10.1109\/isca.1999.765940","DOI":"10.1109\/ISCA.1999.765940"},{"key":"43","doi-asserted-by":"crossref","unstructured":"[43] M.H. Lipasti, C.B. Wilkerson, and J.P. Shen, \u201cValue locality and load value prediction,\u201d Proc. Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pp.138-147, 1996. 10.1145\/237090.237173","DOI":"10.1145\/237090.237173"},{"key":"44","doi-asserted-by":"crossref","unstructured":"[44] M. Cintra, J.F. Mart\u00ednez, and J. Torrellas, \u201cArchitectural support for scalable speculative parallelization in shared-memory multiprocessors,\u201d Proc. 27th Annual International Symposium on Computer Architecture, pp.13-24, 2000. 10.1109\/isca.2000.854373","DOI":"10.1109\/ISCA.2000.854373"},{"key":"45","doi-asserted-by":"crossref","unstructured":"[45] H. Akkary and M.A. Driscoll, \u201cA dynamic multithreading processor,\u201d Proc. 31st Annual ACM\/IEEE International Symposium on Microarchitecture, pp.226-236, 1998. 10.1109\/micro.1998.742784","DOI":"10.1109\/MICRO.1998.742784"},{"key":"46","doi-asserted-by":"crossref","unstructured":"[46] M. Prvulovic, M.J. Garzar\u00e1n, L. Rauchwerger, and J. Torrellas, \u201cRemoving architectural bottlenecks to the scalability of speculative parallelization,\u201d Proc. 28th Annual International Symposium on Computer Architecture, pp.204-215, 2001. 10.1109\/isca.2001.937450","DOI":"10.1109\/ISCA.2001.937450"},{"key":"47","doi-asserted-by":"publisher","unstructured":"[47] V. Krishnan and J. Torrellas, \u201cA chip-multiprocessor architecture with speculative multithreading,\u201d IEEE Trans. Comput., vol.48, no.9, pp.866-880, Sept. 1999. 10.1109\/12.795218","DOI":"10.1109\/12.795218"},{"key":"48","doi-asserted-by":"crossref","unstructured":"[48] M.J. Garzar\u00e1n, M. Prvulovic, J.M. Llaber\u00eda, V. Vi\u00f1als, L.Rauchwerger, and J. Torrellas, \u201cTradeoffs in buffering memory state for thread-level speculation in multiprocessors,\u201d Proc. 9th International Symposium on High-Performance Computer Architecture, pp.191-202, 2003. 10.1109\/hpca.2003.1183537","DOI":"10.1109\/HPCA.2003.1183537"},{"key":"49","doi-asserted-by":"crossref","unstructured":"[49] C. Zilles and G. Sohi, \u201cExecution-based prediction using speculative slices,\u201d Proc. 28th Annual International Symposium on Computer Architecture, pp.2-13, 2001. 10.1109\/isca.2001.937426","DOI":"10.1109\/ISCA.2001.937426"},{"key":"50","doi-asserted-by":"crossref","unstructured":"[50] J. Dundas and T. Mudge, \u201cImproving data cache performance by pre-executing instructions under a cache miss,\u201d Proc. 11th International Conference on Supercomputing, pp.68-75, 1997.","DOI":"10.1145\/263580.263597"},{"key":"51","doi-asserted-by":"crossref","unstructured":"[51] O. Mutlu, J. Stark, C. Wilkerson, and Y.N. Patt, \u201cRunahead execution: an alternative to very large instruction windows for out-of-order processors,\u201d Proc. Ninth International Symposium on High-Performance Computer Architecture, pp.129-140, 2003. 10.1109\/hpca.2003.1183532","DOI":"10.1109\/HPCA.2003.1183532"},{"key":"52","doi-asserted-by":"crossref","unstructured":"[52] J.D. Collins, D.M. Tullsen, H. Wang, and J.P. Shen, \u201cDynamic speculative precomputation,\u201d Proc. 34th Annual ACM\/IEEE International Symposium on Microarchitecture, pp.306-317, 2001. 10.1109\/micro.2001.991128","DOI":"10.1109\/MICRO.2001.991128"},{"key":"53","doi-asserted-by":"crossref","unstructured":"[53] O. Mutlu, H. Kim, and Y.N. Patt, \u201cTechniques for efficient processing in runahead execution engines,\u201d Proc. 32nd Annual International Symposium on Computer Architecture, pp.370-381, 2005. 10.1109\/isca.2005.49","DOI":"10.1109\/ISCA.2005.49"},{"key":"54","doi-asserted-by":"publisher","unstructured":"[54] J.D. Collins, H. Wang, D.M. Tullsen, C. Hughes, Y.-F. Lee, D. Lavery, and J.P. Shen, \u201cSpeculative precomputation: Long-range prefetching of delinquent loads,\u201d ACM SIGARCH Computer Architecture News, vol.29, no.2, pp.14-25, 2001. 10.1145\/384285.379248","DOI":"10.1145\/384285.379248"},{"key":"55","doi-asserted-by":"crossref","unstructured":"[55] H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, \u201cNeural acceleration for general-purpose approximate programs,\u201d Proc. 2012 45th Annual IEEE\/ACM International Symposium on Microarchitecture, pp.449-460, 2012. 10.1109\/micro.2012.48","DOI":"10.1109\/MICRO.2012.48"},{"key":"56","doi-asserted-by":"crossref","unstructured":"[56] H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, \u201cArchitecture support for disciplined approximate programming,\u201d Proc.Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems, pp.301-312, 2012. 10.1145\/2150976.2151008","DOI":"10.1145\/2150976.2151008"},{"key":"57","doi-asserted-by":"crossref","unstructured":"[57] M. Samadi, J. Lee, D.A. Jamshidi, A. Hormati, and S. Mahlke, \u201cSage: Self-tuning approximation for graphics engines,\u201d Proc. 46th Annual IEEE\/ACM International Symposium on Microarchitecture, pp.13-24, 2013. 10.1145\/2540708.2540711","DOI":"10.1145\/2540708.2540711"},{"key":"58","doi-asserted-by":"crossref","unstructured":"[58] M. Samadi, D.A. Jamshidi, J. Lee, and S. Mahlke, \u201cParaprox: Pattern-based approximation for data parallel applications,\u201d Proc. 19th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.35-50, 2014. 10.1145\/2541940.2541948","DOI":"10.1145\/2541940.2541948"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E101.D\/12\/E101.D_2018PAP0003\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,11,6]],"date-time":"2019-11-06T07:40:10Z","timestamp":1573026010000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E101.D\/12\/E101.D_2018PAP0003\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12,1]]},"references-count":58,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2018]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2018pap0003","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,12,1]]}}}