{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:46:17Z","timestamp":1772120777242,"version":"3.50.1"},"reference-count":16,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2020,4,1]]},"DOI":"10.1587\/transinf.2019edl8175","type":"journal-article","created":{"date-parts":[[2020,3,31]],"date-time":"2020-03-31T22:24:36Z","timestamp":1585693476000},"page":"892-895","source":"Crossref","is-referenced-by-count":3,"title":["Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge"],"prefix":"10.1587","volume":"E103.D","author":[{"given":"Kazuteru","family":"NAMBA","sequence":"first","affiliation":[{"name":"Graduate School of Engineering, Chiba University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, \u201cImpact of scaling on neutron-induced soft error in SRAMs from a 250nm to a 22nm design rule,\u201d IEEE Trans. Electron Devices, vol.57, no.7, pp.1527-1538, July 2010. 10.1109\/ted.2010.2047907","DOI":"10.1109\/TED.2010.2047907"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] E. Fujiwara, Code design for dependable systems: theory and practical applications, Wiley-Interscience, 2006.","DOI":"10.1002\/0471792748"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] S. Mitra, M. Zhang, S. Waqas, N. Seifert, B. Gill, and K.S. Kim, \u201cCombinational logic soft error correction,\u201d IEEE Int&apos;l Test Conf., pp.824-832, 2006. 10.1109\/test.2006.297681","DOI":"10.1109\/TEST.2006.297681"},{"key":"4","unstructured":"[4] Y. Komatsu, Y. Arima, T. Fujimoto, T. Yamashita, and K. Ishibashi, \u201cA soft-error hardened latch scheme for SoC in a 90nm technology and beyond,\u201d IEEE Custom Integr. Circuit Conf., pp.329-332, 2004. 10.1109\/cicc.2004.1358812"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] T. Calin, M. Nicolaidis, and R. Velazco, \u201cUpset hardened memory design for submicron CMOS technology,\u201d IEEE Trans. Nuclear Sci., vol.43, no.6, pp.2874-2878, Dec. 1996. 10.1109\/23.556880","DOI":"10.1109\/23.556880"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] S. Campitelli, M. Ottavi, S. Pontarelli, A. Marchioro, D. Felici, and F. Lombardi, \u201cF-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments,\u201d IEEE Int&apos;l Symp. Defect &amp; Fault Tolerance VLSI &amp; Nanotechnol. Syst., pp.107-111, 2013. doi: 10.1109\/DFT.2013.6653591. 10.1109\/dft.2013.6653591","DOI":"10.1109\/DFT.2013.6653591"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] N. Eftaxiopoulos, N. Axelos, G. Zervakis, K. Tsoumanis, and K. Pekmestzi, \u201cDelta DICE: a double node upset resilient latch,\u201d IEEE Int&apos;l Midwest Symp. Circuit &amp; Syst., 2015. doi: 10.1109\/MWSCAS.2015.7282145. 10.1109\/mwscas.2015.7282145","DOI":"10.1109\/MWSCAS.2015.7282145"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] N. Eftaxiopoulos, N. Axelos, and K. Pekmestzi, \u201cDONUT: a double node upset tolerant latch,\u201d IEEE Comput. Soc. Annu.Symp. VLSI, pp.509-514, 2015. doi: 10.1109\/ISVLSI.2015.72. 10.1109\/isvlsi.2015.72","DOI":"10.1109\/ISVLSI.2015.72"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] A. Watkins and S. Tragouodas, \u201cA highly robust double node upset tolerant latch,\u201d IEEE Int&apos;l Symp. Defect &amp; Fault Tolerance VLSI &amp; Nanotechnol. Syst., pp.15-20, 2016. doi: 10.1109\/DFT.2016.7684062. 10.1109\/dft.2016.7684062","DOI":"10.1109\/DFT.2016.7684062"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] R. Naseer and J. Draper, \u201cThe DF-DICE storage element for immunity to soft errors,\u201d IEEE Int&apos;l Midwest Symp. Circuit &amp; Syst., pp.303-306, 2005. 10.1109\/mwscas.2005.1594099","DOI":"10.1109\/MWSCAS.2005.1594099"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] A. Maru, H. Shindou, T. Ebihara, A. Makihara, T. Hirao, and S. Kuboyama, \u201cDICE-based flip-flop with SET pulse discriminator on a 90nm bulk CMOS process,\u201d IEEE Trans. Nucl. Sci., vol.57, no.6, pp.3602-3608, Dec. 2010. 10.1109\/tns.2010.2086481","DOI":"10.1109\/TNS.2010.2086481"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] A. Balijepalli, S. Sinha, and Y. Cao, \u201cCompact modeling of carbon nanotube transistor for early stage process-design exploration,\u201d Int&apos;l Symp. Low Power Electronics &amp; Des., pp.2-7, 2007. 10.1145\/1283780.1283783","DOI":"10.1145\/1283780.1283783"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] W. Zhao and Y. Cao, \u201cNew generation of predictive technology model for sub-45nm early design exploration,\u201d IEEE Trans. Electron Devices, vol.53, no.11, pp.2816-2823, Nov. 2006. 10.1109\/ted.2006.884077","DOI":"10.1109\/TED.2006.884077"},{"key":"14","unstructured":"[14] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, \u201cNew paradigm of predictive MOSFET and interconnect modeling for early circuit simulation,\u201d IEEE Custom Integr. Circuit Conf., pp.201-204, 2000. 10.1109\/cicc.2000.852648"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] K. Namba, T. Ikeda, and H. Ito, \u201cConstruction of SEU tolerant flip-flops allowing enhanced scan delay fault testing,\u201d IEEE Trans. Very Large Scale Integr. Syst., vol.18, no.9, pp.1265-1276, Sept. 2010. 10.1109\/tvlsi.2009.2022083","DOI":"10.1109\/TVLSI.2009.2022083"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] N. Horita and K. Namba, \u201cMeasurements of critical charge around rising edge of clock signal,\u201d IEEE Int&apos;l Conf. Consum. Electron. Taiwan, 2018. doi:10.1109\/ICCE-China.2018.8448827. 10.1109\/ICCE-China.2018.8448827","DOI":"10.1109\/ICCE-China.2018.8448827"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E103.D\/4\/E103.D_2019EDL8175\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,10,20]],"date-time":"2022-10-20T03:44:44Z","timestamp":1666237484000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E103.D\/4\/E103.D_2019EDL8175\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4,1]]},"references-count":16,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2019edl8175","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4,1]]}}}