{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,5,19]],"date-time":"2023-05-19T21:15:51Z","timestamp":1684530951661},"reference-count":20,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2020,11,1]]},"DOI":"10.1587\/transinf.2019edp7235","type":"journal-article","created":{"date-parts":[[2020,10,31]],"date-time":"2020-10-31T22:13:15Z","timestamp":1604182395000},"page":"2289-2301","source":"Crossref","is-referenced-by-count":2,"title":["FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST"],"prefix":"10.1587","volume":"E103.D","author":[{"given":"Hanan T.","family":"Al-AWADHI","sequence":"first","affiliation":[{"name":"Dept. of Computer Science, Ehime University"}],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Tomoki","family":"AONO","sequence":"additional","affiliation":[{"name":"Dept. of Computer Science, Ehime University"}],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Senling","family":"WANG","sequence":"additional","affiliation":[{"name":"Dept. of Computer Science, Ehime University"}],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Yoshinobu","family":"HIGAMI","sequence":"additional","affiliation":[{"name":"Dept. of Computer Science, Ehime University"}],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Hiroshi","family":"TAKAHASHI","sequence":"additional","affiliation":[{"name":"Dept. of Computer Science, Ehime University"}],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Hiroyuki","family":"IWATA","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Yoichi","family":"MAEDA","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocab":"crossref"}]},{"given":"Jun","family":"MATSUSHIMA","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocab":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] ISO26262-5:2011, \u201cRoad vehicles-Functional Safety-Part 5: Product development at the hardware level,\u201d Online Browsing Platform, https:\/\/www.iso.org\/obp\/ui\/#iso:std:iso:26262:-5:ed-1:v1:en, accessed Nov. 10. 2018."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H. Iwata and J. Matsushima, \u201cMulti-configuration Scan Structure for Various Purposes,\u201d Proc. IEEE 25th Asian Test Symposium,Hiroshima, p.131, Nov. 2016. DOI: 10.1109\/ATS.2016.32 10.1109\/ats.2016.32","DOI":"10.1109\/ATS.2016.32"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] N.A. Touba, \u201cSurvey of Test Vector Compaction Techniques,\u201d IEEE Des. Test. Comput., vol.23, no.4, pp.294-303, April 2006. DOI: 10.1109\/MDT.2006.105 10.1109\/mdt.2006.105","DOI":"10.1109\/MDT.2006.105"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] F. Zhang, D. Hwong, Y. Sun, A. Garcia, S. Alhelaly, G. Shofner, L. Winemberg, and J. Dworak, \u201cPutting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture,\u201d Proc. IEEE Int&apos;l Test Conf., Fort Worth, pp.1-10, 2016. DOI: 10.1109\/TEST.2016.7805828 10.1109\/test.2016.7805828","DOI":"10.1109\/TEST.2016.7805828"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] G. Mrugalski, J. Rajski, J. Solecki, J. Tyszer, and C. Wang, \u201cTrimodal Scan-Based Test Paradigm,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.25, no.3, pp.1112-1125, March 2017. DOI: 10.1109\/TVLSI.2016.2608984 10.1109\/tvlsi.2016.2608984","DOI":"10.1109\/TVLSI.2016.2608984"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] S. Milewski, N. Mukherjee, J. Rajski, J. Solecki, J. Tyszer, and J. Zawada, \u201cFull-scan LBIST with Capture-per-cycle Hybrid Test Points,\u201d Proc. IEEE Int&apos;l Test Conf., Fort Worth, pp.1-9, 2017. DOI: 10.1109\/TEST.2017.8242036 10.1109\/test.2017.8242036","DOI":"10.1109\/TEST.2017.8242036"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] P. Girard, N. Bicolici, and X. Wen, Power-Aware Testing and Test Strategies for Low Power Devices, Springer, ISBN 978-1-4419-0927-5, New York, 2010.","DOI":"10.1007\/978-1-4419-0928-2"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] H.-C. Tsai, K.-T. Cheng, and S. Bhawmik, \u201cImproving the Test Quality for Scan-based BIST Using a General Test Application Scheme,\u201d Proc. Design Automation Conf., New Orleans, pp.748-753, June 1999. DOI: 10.1109\/DAC.1999.782113 10.1109\/DAC.1999.782113","DOI":"10.1109\/DAC.1999.782113"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] Y. Huang, I. Pomeranz, S.M. Reddy, and J. Rajski, \u201cImproving the proportion of At-Speed Tests in Scan BIST,\u201d Int&apos;l. Conf. on Computer Aided Design, San Jose, pp.459-463, Nov. 2000. DOI: 10.1109\/ICCAD.2000.896514 10.1109\/iccad.2000.896514","DOI":"10.1109\/ICCAD.2000.896514"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S. Kajihara, M. Matsuzono, H. Yamaguchi, Y. Sato, K. Miyase, and X. Wen, \u201cOn Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test,\u201d Proc. Int&apos;l. Symposium on Com. and Inf. Tech. (ISCIT), Tokyo, pp.723-726, Oct. 2010. DOI: 10.1109\/ISCIT.2010.5665084 10.1109\/iscit.2010.5665084","DOI":"10.1109\/ISCIT.2010.5665084"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] I. Pomeranz, \u201cA Multicycle Test Set Based on a Two-Cycle Test Set with Constant Primary Input Vectors,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.34, no.7, pp.1124-1132, July 2015. DOI: 10.1109\/TCAD.2015.2408257 10.1109\/tcad.2015.2408257","DOI":"10.1109\/TCAD.2015.2408257"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Rearick, \u201cToo Much Delay Fault Coverage is a Bad Thing,\u201d Proc. Int&apos;l Test Conf., Baltimore, MD, pp.624-633, 2001. DOI: 10.1109\/TEST.2001.966682 10.1109\/test.2001.966682","DOI":"10.1109\/TEST.2001.966682"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] Y. Sato, H. Yamaguchi, M. Matsuzono, and S. Kajihara, \u201cMulti-Cycle Test with Partial Observation on Scan-Based BIST Structure,\u201d Proc. IEEE Asian Test Symposium, New Delhi, pp.54-59, 2011. DOI: 10.1109\/ATS.2011.34 10.1109\/ats.2011.34","DOI":"10.1109\/ATS.2011.34"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] S. Wang, H.T. Al-Awadhi, S. Hamada, Y. Higami, H. Takahashi, H. Iwata, and J. Matsushima, \u201cStructure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation,\u201d Proc. IEEE Asian Test Symposium,Hiroshima, pp.209-214, Nov. 2016. DOI: 10.1109\/ATS.2016.40 10.1109\/ats.2016.40","DOI":"10.1109\/ATS.2016.40"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] S. Wang, Y. Higami, H. Iwata, J. Matsushima, and H. Takahashi, \u201cAutomotive Functional Safety Assurance by POST with Sequential Observation,\u201d IEEE Design &amp; Test Magazine, vol.35, no.3, pp.39-45, June 2018. DOI: 10.1109\/MDAT.2018.2799801 10.1109\/mdat.2018.2799801","DOI":"10.1109\/MDAT.2018.2799801"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] S. Wang, Y. Higami, H. Takahashi, H. Iwata, Y. Maeda, and J.Matsushima, \u201cFault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262,\u201d Proc. IEEE 23rd European Test Symposium, Bremen, pp.1-2, 2018. DOI: 10.1109\/ETS.2018.8400707 10.1109\/ets.2018.8400707","DOI":"10.1109\/ETS.2018.8400707"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] E.K. Moghaddam, J. Rajski, S.M. Reddy, and M. Kassab, \u201cAt-Speed Scan Test with Low Switching Activity,\u201d Proc. IEEE 28th VLSI Test Symposium, Santa Cruz, pp.177-182, April 2010. DOI: 10.1109\/VTS.2010.5469580 10.1109\/vts.2010.5469580","DOI":"10.1109\/VTS.2010.5469580"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] Y. Sato, S. Wang, T. Kato, K. Miyase, and S. Kajihara, \u201cLow Power BIST for Scan-Shift and Capture Power,\u201d Proc. IEEE Asian Test Symposium, Niigata, pp.173-178, 2012. DOI: 10.1109\/ ATS.2012.27 10.1109\/ats.2012.27","DOI":"10.1109\/ATS.2012.27"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] S. Wang, T. Aono, Y. Higami, H. Takahashi, H. Iwata, Y. Maeda, and J. Matsushima, \u201cCapture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-Cycle Test in Logic BIST,\u201d Proc. IEEE Asian Test Symposium, Hefei, pp.155-160, 2018. DOI:10.1109\/ats.2018.00038 10.1109\/ats.2018.00038","DOI":"10.1109\/ATS.2018.00038"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] K. Yoon, \u201cA Reconciliation among Discrete Compromise Solutions,\u201d Journal of Operational Research Society, vol.38, no.3, pp.277-286, 1987. DOI: 10.2307\/2581948 10.2307\/2581948","DOI":"10.2307\/2581948"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E103.D\/11\/E103.D_2019EDP7235\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,7]],"date-time":"2020-11-07T03:24:55Z","timestamp":1604719495000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E103.D\/11\/E103.D_2019EDP7235\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,1]]},"references-count":20,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2019edp7235","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,11,1]]}}}