{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,31]],"date-time":"2024-08-31T23:10:18Z","timestamp":1725145818100},"reference-count":26,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2021,6,1]]},"DOI":"10.1587\/transinf.2020edp7042","type":"journal-article","created":{"date-parts":[[2021,5,31]],"date-time":"2021-05-31T22:39:32Z","timestamp":1622500772000},"page":"816-827","source":"Crossref","is-referenced-by-count":2,"title":["On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption"],"prefix":"10.1587","volume":"E104.D","author":[{"given":"Yucong","family":"ZHANG","sequence":"first","affiliation":[{"name":"Kyushu Institute of Technology"}]},{"given":"Stefan","family":"HOLST","sequence":"additional","affiliation":[{"name":"Kyushu Institute of Technology"}]},{"given":"Xiaoqing","family":"WEN","sequence":"additional","affiliation":[{"name":"Kyushu Institute of Technology"}]},{"given":"Kohei","family":"MIYASE","sequence":"additional","affiliation":[{"name":"Kyushu Institute of Technology"}]},{"given":"Seiji","family":"KAJIHARA","sequence":"additional","affiliation":[{"name":"Kyushu Institute of Technology"}]},{"given":"Jun","family":"QIAN","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Inc."}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, July 2006. 10.1016\/B978-0-12-370597-6.X5000-8","DOI":"10.1016\/B978-012370597-6\/50006-8"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] J. Saxena, K.M. Butler, V.B. Jayaram, S. Kundu, N.V. Arvind, P. Sreeprakash, and M. Hachinger, \u201cA case study of IR-Drop in structured at-speed testing,\u201d Proc. IEEE Int'l Test Conf., pp.1098-1104, Sept. 2003. 10.1109\/TEST.2003.1271098","DOI":"10.1109\/TEST.2003.1271098"},{"key":"3","unstructured":"[3] T. Yoshida and M. Watari, \u201cMD-SCAN method for low power scan testing,\u201d Proc. IEEE Asian Test Symp., pp.80-85, Nov. 2002. 10.1109\/ATS.2002.1181690"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] R. Wang, B. Bhaskaran, K. Natarajan, A. Abdollahian, K. Narayanun, K. Chakrabarty, and A. Sanghani, \u201cA programmable method for low-power scan shift in SoC integrated circuits,\u201d Proc. IEEE VLSI Test Symp., April 2016. 10.1109\/VTS.2016.7477289","DOI":"10.1109\/VTS.2016.7477289"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] P. Girard, N. Nicolici, and X. Wen, eds., Power-Aware Testing and Test Strategies for Low Power Devices, Springer, Oct. 2010. 10.1007\/978-1-4419-0928-2","DOI":"10.1007\/978-1-4419-0928-2"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] M. Tehranipoor and K.M. Butler, \u201cPower supply noise: A survey on effects and research,\u201d IEEE Des. Test, vol.27, no.2, pp.51-67, March 2010. 10.1109\/MDT.2010.52","DOI":"10.1109\/MDT.2010.52"},{"key":"7","unstructured":"[7] X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K.K. Saluja, and K. Kinoshita, \u201cOn low-capture-power test generation for scan testing,\u201d Proc. IEEE VLSI Test Symp., pp.265-270, May 2005. 10.1109\/VTS.2005.60"},{"key":"8","unstructured":"[8] R. Sankaralingam, R.R. Oruganti, and N.A. Touba, \u201cStatic compaction techniques to control scan vector power dissipation,\u201d Proc. IEEE VLSI Test Symp., pp.35-40, April 2000. 10.1109\/VTEST.2000.843824"},{"key":"9","unstructured":"[9] R. Sankaralingam and N.A. Touba, \u201cControlling peak power during scan testing,\u201d Proc. IEEE VLSI Test Symp., pp.153-159, May 2002. 10.1109\/VTS.2002.1011127"},{"key":"10","unstructured":"[10] K.M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain, and J. Lewis, \u201cMinimizing power consumption in scan testing: Pattern generation and DFT techniques,\u201d Proc. IEEE Int'l Test Conf., pp.355-364, Oct. 2004. 10.1109\/TEST.2004.1386971"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, and H.-J. Wunderlich, \u201cMinimizing peak power consumption during scan testing: Structural technique for don't care bits assignment,\u201d Proc. Ph.D. Research in Microelectronics and Electronics, pp.65-68, June 2006. 10.1109\/RME.2006.1689897","DOI":"10.1109\/RME.2006.1689897"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] H.-T. Lin and J.C.-M. Li, \u201cSimultaneous capture and shift power reduction test pattern generator for scan testing,\u201d IET Computers Digital Techniques, vol.2, no.2, pp.132-141, March 2008. 10.1049\/iet-cdt:20070088","DOI":"10.1049\/iet-cdt:20070088"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] S. Gerstendorfer and H.J. Wunderlich, \u201cMinimized power consumption for scan-based BIST,\u201d J. Electronic Testing: Theory and Applications, vol.16, no.3, pp.203-212, June 2000. 10.1023\/A:1008383013319","DOI":"10.1023\/A:1008383013319"},{"key":"14","unstructured":"[14] L. Whetsel, \u201cAdapting scan architectures for low power operation,\u201d Proc. IEEE Int'l Test Conf., pp.863-872, Oct. 2000. 10.1109\/TEST.2000.894297"},{"key":"15","unstructured":"[15] R. Sankaralingam, B. Pouya, and N.A. Touba, \u201cReducing power dissipation during test using scan chain disable,\u201d Proc. IEEE VLSI Test Symp., pp.319-324, April 2001. 10.1109\/VTS.2001.923456"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, and L.-T. Wang, \u201cOn achieving capture power safety in at-speed scan-based logic BIST,\u201d Proc. IEEE Asian Test Symp., pp.19-24, Nov. 2013. 10.1109\/ATS.2013.14","DOI":"10.1109\/ATS.2013.14"},{"key":"17","unstructured":"[17] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, \u201cA gated clock scheme for low power scan testing of logic ICs or embedded cores,\u201d Proc. IEEE Asian Test Symp., pp.253-258, Nov. 2001. 10.1109\/ATS.2001.990291"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] Y. Yamato, X. Wen, M.A. Kochte, K. Miyase, S. Kajihara, and L.-T. Wang, \u201cLCTI-SS: Low-clock-tree-impact scan segmentation for avoiding shift timing failures in scan testing,\u201d IEEE Des. Test, vol.30, no.4, pp.60-70, Aug. 2013. 10.1109\/MDT.2012.2221152","DOI":"10.1109\/MDT.2012.2221152"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] P. Rosinger, B.M. Al-Hashimi, and N. Nicolici, \u201cScan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.23, no.7, pp.1142-1153, July 2004. 10.1109\/TCAD.2004.829797","DOI":"10.1109\/TCAD.2004.829797"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] Y.-C. Huang, M.-H. Tsai, W.-S. Ding, J.C.-M. Li, M.-T. Chang, M.-H. Tsai, C.-M. Tseng, and H.-C. Li, \u201cTest clock domain optimization to avoid scan shift failure due to flip-flop simultaneous triggering,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.32, no.4, pp.644-652, April 2013. 10.1109\/TCAD.2012.2228741","DOI":"10.1109\/TCAD.2012.2228741"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] N. Ahmed, M. Tehranipoor, and V. Jayaram, \u201cTransition delay fault test pattern generation considering supply voltage noise in a SOC design,\u201d Proc. 44th ACM\/IEEE Design Automation Conf., pp.533-538, June 2007. 10.1145\/1278480.1278616","DOI":"10.1109\/DAC.2007.375222"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] J. Ma, J. Lee, and M. Tehranipoor, \u201cLayout-aware pattern generation for maximizing supply noise effects on critical paths,\u201d Proc. IEEE VLSI Test Symp., pp.221-226, May 2009. 10.1109\/VTS.2009.45","DOI":"10.1109\/VTS.2009.45"},{"key":"23","unstructured":"[23] M.-F. Wu, K.-H. Tsai, W.-T. Cheng, H.-C. Pan, J.-L. Huang, and A. Kifli, \u201cA scalable quantitative measure of IR-drop effects for scan pattern generation,\u201d Proc. IEEE Int'l Conf. on Comput.-Aided Design, pp.162-167, Nov. 2010. 10.1109\/ICCAD.2010.5654130"},{"key":"24","unstructured":"[24] T.R. Jensen and B. Toft, eds., Graph Coloring Problems, John Wiley & Sons, 2011. 10.1002\/9781118032497"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] R. Goldman, K. Bartleson, T. Wood, K. Kranen, C. Cao, V. Melikyan, and G. Markosyan, \u201cSynopsys' open educational design kit: Capabilities, deployment and future,\u201d Proc. IEEE Int'l Conf. on Microelectronic Systems Education, pp.20-24, July 2009. 10.1109\/MSE.2009.5270840","DOI":"10.1109\/MSE.2009.5270840"},{"key":"26","doi-asserted-by":"publisher","unstructured":"[26] D.L. Berre and A. Parrain, \u201cThe SAT4J library, release 2.2, System description,\u201d J. Satisfiability, Boolean Modeling and Computation, vol.7, pp.59-64, 2010. 10.3233\/SAT190075","DOI":"10.3233\/SAT190075"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E104.D\/6\/E104.D_2020EDP7042\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,31]],"date-time":"2024-08-31T22:26:32Z","timestamp":1725143192000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E104.D\/6\/E104.D_2020EDP7042\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,1]]},"references-count":26,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2020edp7042","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"type":"print","value":"0916-8532"},{"type":"electronic","value":"1745-1361"}],"subject":[],"published":{"date-parts":[[2021,6,1]]}}}