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Lecun, Y. Bengio, and G. Hinton, \u201cDeep learning,\u201d Nature, vol.521, pp.436-444, 5 2015. 10.1038\/nature14539","DOI":"10.1038\/nature14539"},{"key":"2","unstructured":"[2] S. Han, J. Pool, J. Tran, and W. Dally, \u201cLearning both weights and connections for efficient neural network,\u201d Advances in neural information processing systems, pp.1135-1143, 2015."},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Shimoda, Y. Sada, and H. Nakahara, \u201cFilter-wise pruning approach to FPGA implementation of fully convolutional network for semantic segmentation,\u201d Proc. 15th International Symposium on Applied Reconfigurable Computing, pp.371-386, Darmstadt, Germany, April 2019. 10.1007\/978-3-030-17227-5_26","DOI":"10.1007\/978-3-030-17227-5_26"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] A. Krizhevsky, I. Sutskever, and G.E. Hinton, \u201cImagenet classification with deep convolutional neural networks,\u201d Proc. 25th Int. Conf. Neural Information Processing Systems-Volume 1, NIPS&apos;12, (USA), pp.1097-1105, Curran Associates Inc., 2012. 10.1145\/3065386","DOI":"10.1145\/3065386"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] J. Li, G. Yan, W. Lu, S. Jiang, S. Gong, J. Wu, and X. Li, \u201cCcr: A concise convolution rule for sparse neural network accelerators,\u201d 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp.189-194, March 2018. 10.23919\/DATE.2018.8342001","DOI":"10.23919\/DATE.2018.8342001"},{"key":"6","unstructured":"[6] G. Hinton, O. Vinyals, and J. Dean, \u201cDistilling the knowledge in a neural network,\u201d arXiv preprint arXiv:1503.02531, 2015."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] G.J. Brostow, J. Fauqueur, and R. Cipolla, \u201cSemantic object classes in video: A high-definition ground truth database,\u201d vol.30, no.2, pp.88-97, Jan. 2009. 10.1016\/j.patrec.2008.04.005","DOI":"10.1016\/j.patrec.2008.04.005"},{"key":"8","unstructured":"[8] S. Tokui, K. Oono, S. Hido, and J. Clayton, \u201cChainer: a next-generation open source framework for deep learning,\u201d Proc. Workshop on Machine Learning Systems (LearningSys) in The Twenty-ninth Annual Conference on Neural Information Processing Systems (NIPS), pp.1-6, 2015."},{"key":"9","unstructured":"[9] M. Zhu and S. Gupta, \u201cTo prune, or not to prune: exploring the efficacy of pruning for model compression,\u201d CoRR, vol.abs\/1710.01878, 2017."},{"key":"10","unstructured":"[10] D. Molchanov, A. Ashukha, and D. Vetrov, \u201cVariational dropout sparsifies deep neural networks,\u201d arXiv preprint arXiv:1701.05369, 2017."},{"key":"11","unstructured":"[11] J.M. Alvarez and M. Salzmann, \u201cCompression-aware training of deep networks,\u201d Advances in Neural Information Processing Systems, pp.856-867, 2017."},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Yu, A. Lukefahr, D. Palframan, G. Dasika, R. Das, and S. Mahlke, \u201cScalpel: Customizing dnn pruning to the underlying hardware parallelism,\u201d Proc. 44th Annual International Symposium on Computer Architecture, ISCA &apos;17, (New York, NY, USA), pp.548-560, ACM, 2017. 10.1145\/3079856.3080215","DOI":"10.1145\/3079856.3080215"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] S. Zhang, Z. Du, L. Zhang, H. Lan, S. Liu, L. Li, Q. Guo, T. Chen, and Y. Chen, \u201cCambricon-x: An accelerator for sparse neural networks,\u201d 2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), pp.1-12, Oct. 2016. 10.1109\/MICRO.2016.7783723","DOI":"10.1109\/MICRO.2016.7783723"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] J. Albericio, P. Judd, T. Hetherington, T. Aamodt, N.E. Jerger, and A. Moshovos, \u201cCnvlutin: Ineffectual-neuron-free deep neural network computing,\u201d 2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), pp.1-13, June 2016. 10.1109\/ISCA.2016.11","DOI":"10.1109\/ISCA.2016.11"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] S. Han, X. Liu, H. Mao, J. Pu, A. Pedram, M.A. Horowitz, and W.J. Dally, \u201cEie: efficient inference engine on compressed deep neural network,\u201d 2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), pp.243-254, IEEE, 2016. 10.1109\/ISCA.2016.30","DOI":"10.1109\/ISCA.2016.30"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] C. Deng, S. Liao, Y. Xie, K.K. Parhi, X. Qian, and B. Yuan, \u201cPermdnn: Efficient compressed dnn architecture with permuted diagonal matrices,\u201d 2018 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), pp.189-202, Oct. 2018. 10.1109\/MICRO.2018.00024","DOI":"10.1109\/MICRO.2018.00024"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] X. Zhou, Z. Du, Q. Guo, S. Liu, C. Liu, C. Wang, X. Zhou, L. Li, T. Chen, and Y. Chen, \u201cCambricon-s: Addressing irregularity in sparse neural networks through a cooperative software\/hardware approach,\u201d 2018 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), pp.15-28, Oct. 2018. 10.1109\/MICRO.2018.00011","DOI":"10.1109\/MICRO.2018.00011"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] A. Parashar, M. Rhu, A. Mukkara, A. Puglielli, R. Venkatesan, B. Khailany, J. Emer, S.W. Keckler, and W.J. Dally, \u201cScnn: An accelerator for compressed-sparse convolutional neural networks,\u201d 2017 ACM\/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pp.27-40, June 2017. 10.1145\/3079856.3080254","DOI":"10.1145\/3079856.3080254"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] Z. Yuan, J. Yue, H. Yang, Z. Wang, J. Li, Y. Yang, Q. Guo, X. Li, M. Chang, H. Yang, and Y. Liu, \u201cSticker: A 0.41-62.1 tops\/w 8bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers,\u201d 2018 IEEE Symposium on VLSI Circuits, pp.33-34, June 2018. 10.1109\/VLSIC.2018.8502404","DOI":"10.1109\/VLSIC.2018.8502404"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] J. Wang, Z. Yuan, R. Liu, H. Yang, and Y. Liu, \u201cAn n-way group association architecture and sparse data group association load balancing algorithm for sparse cnn accelerators,\u201d Proc. 24th Asia and South Pacific Design Automation Conference, ASPDAC &apos;19, (New York, NY, USA), pp.329-334, ACM, 2019. 10.1145\/3287624.3287626","DOI":"10.1145\/3287624.3287626"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] C.-Y. Lin and B.-C. Lai, \u201cSupporting compressed-sparse activations and weights on simd-like accelerator for sparse convolutional neural networks,\u201d Proc. 23rd Asia and South Pacific Design Automation Conference, ASPDAC &apos;18, (Piscataway, NJ, USA), pp.105-110, IEEE Press, 2018. 10.1109\/ASPDAC.2018.8297290","DOI":"10.1109\/ASPDAC.2018.8297290"},{"key":"22","unstructured":"[22] B. Lai, J. Pan, and C. Lin, \u201cEnhancing utilization of simd-like accelerator for sparse convolutional neural networks,\u201d IEEE Trans. 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