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Wawrzynek, and K. Asanovi\u0107, \u201cChisel: Constructing hardware in a Scala embedded language,\u201d DAC Design Automation Conference 2012, pp.1212-1221, June 2012. 10.1145\/2228360.2228584","DOI":"10.1145\/2228360.2228584"},{"key":"8","unstructured":"[8] SpinalHDL, \u201cVexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation.\u201d https:\/\/github.com\/SpinalHDL\/VexRiscv."},{"key":"9","unstructured":"[9] SpinalHDL, \u201cSpinalHDL: An open source high-level hardware description language.\u201d https:\/\/github.com\/SpinalHDL\/SpinalHDL."},{"key":"10","unstructured":"[10] RISC-V Foundation, \u201cRISC-V SoftCPU Contest, October 8, 2018.\u201d https:\/\/riscv.org\/2018\/10\/risc-v-contest\/."},{"key":"11","unstructured":"[11] University of California, Berkeley, \u201criscv-mini: Simple RISC-V 3-stage Pipeline in Chisel.\u201d https:\/\/github.com\/ucb-bar\/riscv-mini."},{"key":"12","unstructured":"[12] University of California, Berkeley, \u201cThe Sodor Processor: educational microarchitectures for risc-v isa.\u201d https:\/\/github.com\/ucb-bar\/riscv-sodor."},{"key":"13","unstructured":"[13] University of Cambridge, \u201cClarvi: simple RISC-V processor for teaching.\u201d https:\/\/github.com\/ucam-comparch\/clarvi."},{"key":"14","unstructured":"[14] D.A. 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