{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T09:23:59Z","timestamp":1775467439284,"version":"3.50.1"},"reference-count":25,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2021,12,1]]},"DOI":"10.1587\/transinf.2021pap0002","type":"journal-article","created":{"date-parts":[[2021,11,30]],"date-time":"2021-11-30T22:43:17Z","timestamp":1638312197000},"page":"2029-2039","source":"Crossref","is-referenced-by-count":8,"title":["Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System"],"prefix":"10.1587","volume":"E104.D","author":[{"given":"Kohei","family":"ITO","sequence":"first","affiliation":[{"name":"Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kensuke","family":"IIZUKA","sequence":"additional","affiliation":[{"name":"Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazuei","family":"HIRONAKA","sequence":"additional","affiliation":[{"name":"Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yao","family":"HU","sequence":"additional","affiliation":[{"name":"National Institute of Informatics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michihiro","family":"KOIBUCHI","sequence":"additional","affiliation":[{"name":"National Institute of Informatics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"AMANO","sequence":"additional","affiliation":[{"name":"Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] K. Hironaka, B.A. Akram, and H. Amano, \u201cMulti-FPGA Management on Flow-in-Cloud Prototype System,\u201d 2019 20th IEEE\/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel\/Distributed Computing (SNPD), pp.443-448, 2019. 10.1109\/snpd.2019.8935738","DOI":"10.1109\/SNPD.2019.8935738"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] T. Ueno, T. Miyajima, A. Mondigo, and K. Sano, \u201cHybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA Cluster,\u201d 2019 International Conference on Field-Programmable Technology (ICFPT), pp.363-366, 2019. 10.1109\/icfpt47387.2019.00068","DOI":"10.1109\/ICFPT47387.2019.00068"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] N. Fujita, R. Kobayashi, Y. Yamaguchi, and T. Boku, \u201cParallel Processing on FPGA Combining Computation and Communication in OpenCL Programming,\u201d 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp.479-488, 2019. 10.1109\/ipdpsw.2019.00089","DOI":"10.1109\/IPDPSW.2019.00089"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] N. Fujita, R. Kobayashi, Y. Yamaguchi, T. Ueno, K. Sano, and T. Boku, \u201cPerformance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA,\u201d 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp.450-459, 2020. 10.1109\/ipdpsw50202.2020.00083","DOI":"10.1109\/IPDPSW50202.2020.00083"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] Y. Hu and M. Koibuchi, \u201cOptimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems,\u201d IEICE Transactions on Information and Systems, vol.E102-D, no.2, pp.247-260, 2019. 10.1587\/transinf.2018edp7225","DOI":"10.1587\/transinf.2018EDP7225"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] T. Watanabe, M. Nakao, T. Hiroyasu, T. Otsuka, and M. Koibuchi, \u201cImpact of topology and link aggregation on a PC cluster with Ethernet,\u201d Int. Conf. Cluster Comput., pp.280-285, Sept. 2008. 10.1109\/clustr.2008.4663782","DOI":"10.1109\/CLUSTR.2008.4663782"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] S. Lin and J. Shi, \u201cImproving NoC Performance by Non-contention Ejection Architecture,\u201d 2010 IEEE\/ACIS 9th International Conference on Computer and Information Science, pp.555-558, 2010. 10.1109\/icis.2010.23","DOI":"10.1109\/ICIS.2010.23"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] K. Ito, K. Iizuka, K. Hironaka, Y. Hu, M. Koibuchi, and H. Amano, \u201cImplementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System,\u201d 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW), pp.211-217, 2020. 10.1109\/candarw51189.2020.00049","DOI":"10.1109\/CANDARW51189.2020.00049"},{"key":"9","unstructured":"[9] \u201cIEEE Standard for Information Technology-Local and Metropolitan Area Networks-Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA\/CD) Access Method and Physical Layer Specifications-Aggregation of Multiple Link Segments,\u201d IEEE Std 802.3ad-2000, pp.1-184, June 2000. 10.1109\/ieeestd.2000.91610"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] K. Hironaka, K. Iizuka, A. Ben Ahmed, M.M.I. Ullah, Y. Yamauchi, Y. Sun, M. Yamakura, A. Hiruma, and H. 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Amano, \u201cFiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks,\u201d IEICE Transactions on Information and Systems, vol.E103-D, no.12, pp.2457-2462, 2020. 10.1587\/transinf.2020pap0003","DOI":"10.1587\/transinf.2020PAP0003"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] M.M.I. Ullah, A. Ben Ahmed, and H. Amano, \u201cImplementation of FM-Index Based Pattern Search on a Multi-FPGA System,\u201d Applied Reconfigurable Computing. Architectures, Tools, and Applications, ed. F. Rinc\u00f3n, J. Barba, H.K.H. So, P. Diniz, and J. Caba, Cham, pp.376-391, Springer International Publishing, 2020. 10.1007\/978-3-030-44534-8_28","DOI":"10.1007\/978-3-030-44534-8_28"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] M. Yamakura, K. Hironaka, K. Azegami, K. Musha, and H. Amano, \u201cThe Evaluation of Partial Reconfiguration for a Multi-Board FPGA System FiCSW,\u201d Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019, New York, NY, USA, Association for Computing Machinery, 2019. 10.1145\/3337801.3337805","DOI":"10.1145\/3337801.3337805"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] R. Stefan and K. Goossens, \u201cMulti-path routing in time-division-multiplexed networks on chip,\u201d 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp.109-114, 2009. 10.1109\/vlsisoc.2009.6041339","DOI":"10.1109\/VLSISOC.2009.6041339"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] M. Schoeberl, F. Brandner, J. Spars\u00f8, and E. Kasapaki, \u201cA statically scheduled time-division-multiplexed network-on-chip for real-time systems,\u201d 2012 IEEE\/ACM Sixth International Symposium on Networks-on-Chip, pp.152-160, 2012. 10.1109\/nocs.2012.25","DOI":"10.1109\/NOCS.2012.25"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] K. Azegami, K. Musha, K. Hironaka, A. Ben Ahmed, M. Koibuch, Y. Hu, and H. Amano, \u201cA STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System,\u201d 2019 IEEE 13th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC), pp.328-333, Oct. 2019. 10.1109\/mcsoc.2019.00053","DOI":"10.1109\/MCSoC.2019.00053"},{"key":"18","unstructured":"[18] Y. LeCun, P. Haffner, L. Buttou, and Y. Benio, \u201cObject Recognition with Gradient-Based Learning,\u201d http:\/\/yann.lecun.com\/exdb\/publis\/pdf\/lecun-99.pdf"},{"key":"19","unstructured":"[19] R. Kastner, J. Matai, and S. Neuendorffer, \u201cParallel Programming for FPGAs,\u201d CoRR, vol.abs\/1805.03648, 2018."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] A. Putnam, A.M. Caulfield, E.S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G.P. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P.Y. Xiao, and D. Burger, \u201cA reconfigurable fabric for accelerating large-scale datacenter services,\u201d 2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA), pp.13-24, June 2014. 10.1109\/isca.2014.6853195","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] I. Firmansyah, Y. Yamaguchi, and T. Boku, \u201cPerformance evaluation of Stratix V DE5-Net FPGA board for high performance computing,\u201d 2016 International Conference on Computer, Control, Informatics and its Applications (IC3INA), pp.23-27, 2016. 10.1109\/ic3ina.2016.7863017","DOI":"10.1109\/IC3INA.2016.7863017"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] R. Kobayashi, N. Fujita, Y. Yamaguchi, A. Nakamichi, and T. Boku, \u201cGPU-FPGA Heterogeneous Computing with OpenCL-Enabled Direct Memory Access,\u201d 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp.489-498, 2019. 10.1109\/ipdpsw.2019.00090","DOI":"10.1109\/IPDPSW.2019.00090"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] A.K. Lusala and J.-D. Legat, \u201cA SDM-TDM based circuit-switched router for on-chip networks,\u201d 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), pp.1-8, June 2011. 10.1109\/recosoc.2011.5981514","DOI":"10.1109\/ReCoSoC.2011.5981514"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] S. Liu, A. Jantsch, and Z. Lu, \u201cMultiCS: Circuit switched NoC with multiple sub-networks and sub-channels,\u201d Journal of Systems Architecture, vol.61, no.9, pp.423-434, 2015. 10.1016\/j.sysarc.2015.07.013","DOI":"10.1016\/j.sysarc.2015.07.013"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] J. Sheng, C. Yang, T. Wang, and M. Herbordt, \u201cHigh Performance Dynamic Communication on Reconfigurable Clusters,\u201d 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.219-219, 2018. 10.1109\/fccm.2018.00053","DOI":"10.1109\/FCCM.2018.00053"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E104.D\/12\/E104.D_2021PAP0002\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,13]],"date-time":"2024-09-13T10:27:09Z","timestamp":1726223229000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E104.D\/12\/E104.D_2021PAP0002\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,1]]},"references-count":25,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2021pap0002","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,12,1]]},"article-number":"2021PAP0002"}}