{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T09:23:59Z","timestamp":1775467439281,"version":"3.50.1"},"reference-count":22,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2021,12,1]]},"DOI":"10.1587\/transinf.2021pap0005","type":"journal-article","created":{"date-parts":[[2021,11,30]],"date-time":"2021-11-30T22:44:08Z","timestamp":1638312248000},"page":"2078-2088","source":"Crossref","is-referenced-by-count":10,"title":["A Multi-Tenant Resource Management System for Multi-FPGA Systems"],"prefix":"10.1587","volume":"E104.D","author":[{"given":"Miho","family":"YAMAKURA","sequence":"first","affiliation":[{"name":"Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryousei","family":"TAKANO","sequence":"additional","affiliation":[{"name":"Real World Big-Data Computation Open Innovation Laboratory, National Institute of Advanced Industrial Science and Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akram","family":"BEN AHMED","sequence":"additional","affiliation":[{"name":"Real World Big-Data Computation Open Innovation Laboratory, National Institute of Advanced Industrial Science and Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Midori","family":"SUGAYA","sequence":"additional","affiliation":[{"name":"College of Engineering, Shibaura Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"AMANO","sequence":"additional","affiliation":[{"name":"Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] S. Byma, J.G. Steffan, H. Bannazadeh, A. Leon-Garcia, and P. Chow, \u201cFPGAs in the cloud: Booting virtualized hardware accelerators with OpenStack,\u201d 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, pp.109-116, May 2014. 10.1109\/fccm.2014.42","DOI":"10.1109\/FCCM.2014.42"},{"key":"2","unstructured":"[2] Amazon Web Services, Inc., \u201cAmazon EC2 F1 Instance,\u201d https:\/\/aws.amazon.com\/jp\/ec2\/instance-types\/f1\/"},{"key":"3","unstructured":"[3] A. Khawaja, J. Landgraf, R. Prakash, M. Wei, E. Schkufza, and C.J. Rossbach, \u201cSharing, protection, and compatibility for reconfigurable fabric with AmorphOS,\u201d 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18), Carlsbad, CA, pp.107-127, USENIX Association, Oct. 2018."},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Z. Istv\u00e1n, G. Alonso, and A. Singla, \u201cProviding multi-tenant services with FPGAs: Case study on a key-value store,\u201d 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp.119-124, 08 2018. 10.1109\/fpl.2018.00029","DOI":"10.1109\/FPL.2018.00029"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] K. Azegami, K. Musha, K. Hironaka, A.B. Ahmed, M. Koibuch, Y. Hu, and H. Amano, \u201cA STDM (static time division multiplexing) switch on a multi-FPGA system,\u201d 2019 IEEE 13th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC), pp.328-333, 2019. 10.1109\/mcsoc.2019.00053","DOI":"10.1109\/MCSoC.2019.00053"},{"key":"6","unstructured":"[6] ETSI, \u201cMobile edge computing: A key technology towards 5G,\u201d ETSI White Paper no.11."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] A. Vaishnav, K.D. Pham, and D. Koch, \u201cA survey on FPGA virtualization,\u201d Proc. FPL 2018, Sept. 2018. 10.1109\/fpl.2018.00031","DOI":"10.1109\/FPL.2018.00031"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] Y. Hu and M. Koibuchi, \u201cOptimizing slot utilization and network topology for communication pattern on circuit-switched parallel computing systems,\u201d IEICE Trans. Inf. & Syst., vol.E102-D, pp.247-260, Feb. 2019. 10.1587\/transinf.2018edp7225","DOI":"10.1587\/transinf.2018EDP7225"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] K. Ito, K. Iizuka, K. Hironaka, Y. Hu, M. Koibuchi, and H. Amano, \u201cImplementing a multi-ejection switch and making the use of multiple lanes in a circuit-switched multi-FPGA system,\u201d Proc. CANDARW, pp.211-217, Nov. 2010. 10.1109\/candarw51189.2020.00049","DOI":"10.1109\/CANDARW51189.2020.00049"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] K. Hironaka, B.A. Akram, and H. Amano, \u201cMulti-FPGA management on flow-in-cloud prototype system,\u201d 20th IEEE\/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel\/Distributed Computing (SNPD 2019), pp.443-448, July 2019. 10.1109\/snpd.2019.8935738","DOI":"10.1109\/SNPD.2019.8935738"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] A. Vaishnav, K. Pham, and D. Koch, \u201cLive migration for OpenCL FPGA accelerators,\u201d Proc. ICFPT 2018, pp.38-45, Sept. 2018. 10.1109\/fpt.2018.00017","DOI":"10.1109\/FPT.2018.00017"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] A. Fukuhara, S. Shohata, and H. Nishi, \u201cFPGA context-based live migration maintaining network consistency,\u201d Proc. CANDARWS, pp.81-86, 2020. 10.1109\/candarw51189.2020.00027","DOI":"10.1109\/CANDARW51189.2020.00027"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] J. Cui, Q. Deng, X. He, and Z. Gu, \u201cAn efficient algorithm for online management of 2D area of partially reconfigurable FPGAs,\u201d 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1-6, 2007. 10.1109\/date.2007.364579","DOI":"10.1109\/DATE.2007.364579"},{"key":"14","unstructured":"[14] J. Weerasinghe, F. Abel, C. Hagleitner, and A. Herkersdorf, \u201cEnabling FPGAs in hyperscale data centers,\u201d Proc. UIC-ATC-ScalCom, pp.1078-1086, 2015. 10.1109\/uic-atc-scalcom-cbdcom-iop.2015.199"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] K. Fleming and M. Adler, \u201cThe LEAP FPGA operating system,\u201d Proc. FPGAs for Software Programmers 2016, pp.245-258, Sept. 2016. 10.1007\/978-3-319-26408-0_14","DOI":"10.1007\/978-3-319-26408-0_14"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] Z. Wang, S. Zhang, B. He, and W. Zhang, \u201cMelia: A MapReduce framework on OpenCL-based FPGAs,\u201d IEEE Trans. Parallel Distrib. Syst., vol.27, no.12, pp.3547-3560, 2016. 10.1109\/tpds.2016.2537805","DOI":"10.1109\/TPDS.2016.2537805"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] O. Pell, O. Mencer, K.H. Tsoi, and W. Luk, \u201cMaximum performance computing with dataflow engines,\u201d High-Peformance Computing Uning FPGAs, pp.747-774, 2013. 10.1007\/978-1-4614-1791-0_25","DOI":"10.1007\/978-1-4614-1791-0_25"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] A. Putnam, A.M. Caulfield, E.S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G.P. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P.Y. Xiao, and D. Burger, \u201cA reconfigurable fabric for accelerating large-scale datacenter services,\u201d IEEE\/ACM the 41st Annual International Symposium on Computer Architecture (ISCA), pp.13-24, May 2014. 10.1109\/isca.2014.6853195","DOI":"10.1145\/2678373.2665678"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] M. Handa and R. Vemuri, \u201cAn efficient algorithm for finding empty space for online FPGA placement,\u201d Proc. 41st Design Automation Conference, pp.960-965, 2004. 10.1145\/996566.996820","DOI":"10.1145\/996566.996820"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] J. Edmonds, J. Gryz, D. Liang, and R.J. Miller, \u201cMining for empty rectangles in large data sets,\u201d Database Theory \u2014 ICDT 2001, Lecture Notes in Computer Science, vol.1973, pp.174-188, Springer, Berlin, Heidelberg, 2001. 10.1007\/3-540-44503-x_12","DOI":"10.1007\/3-540-44503-X_12"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] K. Bazargan, R. Kastner, and M. Sarrafzadeh, \u201cFast template placement for reconfigurable computing systems,\u201d IEEE Design Test of Computers, vol.17, no.1, pp.68-83, 2000. 10.1109\/54.825678","DOI":"10.1109\/54.825678"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] H. Walder, C. Steiger, and M. Platzner, \u201cFast online task placement on FPGAs: Free space partitioning and 2D-hashing,\u201d Proc. International Parallel and Distributed Processing Symposium, 8 pages, 2003. 10.1109\/ipdps.2003.1213329","DOI":"10.1109\/IPDPS.2003.1213329"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E104.D\/12\/E104.D_2021PAP0005\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,13]],"date-time":"2024-09-13T10:27:28Z","timestamp":1726223248000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E104.D\/12\/E104.D_2021PAP0005\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,1]]},"references-count":22,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2021]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2021pap0005","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,12,1]]},"article-number":"2021PAP0005"}}