{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,7,2]],"date-time":"2022-07-02T05:12:28Z","timestamp":1656738748557},"reference-count":12,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2022,7,1]]},"DOI":"10.1587\/transinf.2022edl8002","type":"journal-article","created":{"date-parts":[[2022,6,30]],"date-time":"2022-06-30T22:18:32Z","timestamp":1656627512000},"page":"1320-1324","source":"Crossref","is-referenced-by-count":0,"title":["A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC"],"prefix":"10.1587","volume":"E105.D","author":[{"given":"Qianqian","family":"WU","sequence":"first","affiliation":[{"name":"School of Computer Science and Technology, Harbin Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhenzhou","family":"JI","sequence":"additional","affiliation":[{"name":"School of Computer Science and Technology, Harbin Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] S. Das and H.K. Kapoor, \u201cVictim retention for reducing cache misses in tiled chip multiprocessors,\u201d Microprocess and Microsystem, vol.38, no.4, pp.263-275, 2014. 10.1016\/j.micpro.2013.11.005","DOI":"10.1016\/j.micpro.2013.11.005"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] M. Zhang and K. Asanovic, \u201cVictim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors,\u201d IEEE International Symposium on Computer Architecture, pp.336-345, IEEE, 2005. 10.1109\/isca.2005.53","DOI":"10.1145\/1080695.1069998"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] B.M. Beckmann, M.R. Marty, and D.A. Wood, \u201cASR: adaptive selective replication for cmp caches,\u201d International Symposium on Microarchitecture, pp.443-454, IEEE, 2006. 10.1109\/micro.2006.10","DOI":"10.1109\/MICRO.2006.10"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] G. Kurian, S. Devadas, and O. Khan, \u201cLocality-aware data replication in the last-level cache,\u201d International Symposium on High-Performance Computer Architecture, pp.1-12, IEEE, 2014. 10.1109\/hpca.2014.6835921","DOI":"10.1109\/HPCA.2014.6835921"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] P.A. Tsai, N. Beckmann, and D. Sanchez, \u201cNexus: a new approach to replication in distributed shared caches,\u201d International Conference on Parallel Architectures and Compilation Techniques, pp.166-179, IEEE, 2017. 10.1109\/pact.2017.42","DOI":"10.1109\/PACT.2017.42"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] J. Albericio, P. Ib\u00e1\u00f1ez and J.M. Llaber\u00eda, \u201cExploiting reuse locality on inclusive shared last-level caches,\u201d ACM Transactions on Architecture and Code Optimization, vol.9, no.4, pp.1-19, 2013. 10.1145\/2400682.2400697","DOI":"10.1145\/2400682.2400697"},{"key":"7","unstructured":"[7] C.-J. Wu, A. Jaleel, W. Hasenplaugh, M. Martonosi, S.C. Steely, and J. Emer, \u201cSHiP: Signature-based Hit Predictor for high performance caching,\u201d International Symposium on Microarchitecture, pp.430-441, IEEE, 2011. 10.1145\/2155620.2155671"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] M.K. Qureshi, A. Jaleel, Y.N. Patt, S.C. Steely, and J. Emer, \u201cAdaptive insertion policies for high performance caching,\u201d International Symposium on Computer Architecture, pp.381-391, ACM, 2007. 10.1145\/1250662.1250709","DOI":"10.1145\/1273440.1250709"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] N. Binkert, B. Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, and D.A. Wood, \u201cThe gem5 simulator,\u201d ACM SIGARCH Computer Architecture News, vol.39, no.2, pp.1-7, 2011. 10.1145\/2024716.2024718","DOI":"10.1145\/2024716.2024718"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] C. Bienia, S. Kumar, J.P. Singh, and K. Li, \u201cThe PARSEC benchmark suite: Characterization and architectural implications,\u201d International Conference on Parallel Architectures and Compilation Techniques, pp.72-81, 2008. 10.1145\/1454115.1454128","DOI":"10.1145\/1454115.1454128"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta, \u201cThe SPLASH-2 programs: characterization and methodological considerations,\u201d ACM SIGARCH Computer Architecture News, vol.23, no.2, pp.24-36, 1995. 10.1145\/225830.223990","DOI":"10.1145\/225830.223990"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] S.J.E. Wilton and N.P. Jouppi, \u201cCACTI: an enhanced cache access and cycle time model,\u201d IEEE Journal of Solid-State Circuits, vol.31, no.5, pp.677-688, 1996. 10.1109\/4.509850","DOI":"10.1109\/4.509850"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E105.D\/7\/E105.D_2022EDL8002\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,2]],"date-time":"2022-07-02T04:40:27Z","timestamp":1656736827000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E105.D\/7\/E105.D_2022EDL8002\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7,1]]},"references-count":12,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2022edl8002","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,7,1]]},"article-number":"2022EDL8002"}}