{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T19:40:14Z","timestamp":1730230814012,"version":"3.28.0"},"reference-count":27,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2023,10,1]]},"DOI":"10.1587\/transinf.2023edp7011","type":"journal-article","created":{"date-parts":[[2023,9,30]],"date-time":"2023-09-30T23:01:15Z","timestamp":1696114875000},"page":"1694-1704","source":"Crossref","is-referenced-by-count":1,"title":["GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting"],"prefix":"10.1587","volume":"E106.D","author":[{"given":"Shiling","family":"SHI","sequence":"first","affiliation":[{"name":"Kyushu Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"HOLST","sequence":"additional","affiliation":[{"name":"Kyushu Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoqing","family":"WEN","sequence":"additional","affiliation":[{"name":"Kyushu Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] L. Ye, Z. Wang, Y. Liu, P. Chen, H. Li, H. Zhang, M. Wu, W. He, L. Shen, Y. Zhang, Z. Tan, Y. Wang, and R. Huang, \u201cThe challenges and emerging technologies for low-power artificial intelligence IoT systems,\u201d IEEE Trans. Circuits Syst. I: Reg. Papers, vol.68, no.12, pp.4821-4834, Aug. 2021. 10.1109\/tcsi.2021.3095622","DOI":"10.1109\/TCSI.2021.3095622"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[3] X. Lin, \u201cLow power testing-what can commercial design-for-test tools provide?,\u201d J. Low Power Electron. Applicat., vol.1, no.3, pp.357-372, Dec. 2011. 10.3390\/jlpea1030357","DOI":"10.3390\/jlpea1030357"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[4] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, San Francisco, CA, USA, 2006.","DOI":"10.1016\/B978-012370597-6\/50006-8"},{"key":"4","unstructured":"[5] X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K.K. Saluja, and K. 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Test Conf., Paper 12.1, Sept. 2011. 10.1109\/test.2011.6139162","DOI":"10.1109\/TEST.2011.6139162"},{"key":"10","doi-asserted-by":"publisher","unstructured":"[11] Y.-C. Huang, M.-H. Tsai, W.-S. Ding, J.C.-M. Li, M.-T. Chang, M.-H. Tsai, C.-M. Tseng, and H.-C. Li, \u201cTest clock domain optimization to avoid scan shift failure due to flip-flop simultaneous triggering,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.32, no.4, pp.644-652, April 2013. 10.1109\/tcad.2012.2228741","DOI":"10.1109\/TCAD.2012.2228741"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[12] S. Gupta, B. Bhaskaran, S. Sarangi, A. Abdollahian, and J. Dworak, \u201cA novel graph-coloring-based solution for low-power scan shift,\u201d IEEE Design Test, vol.37, no.4, pp.14-20, Aug. 2020. 10.1109\/mdat.2020.2968264","DOI":"10.1109\/MDAT.2020.2968264"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[13] M.-F. Wu, H.-C. Pan, T.-H. Wang, J.-L. Huang, K.-H. Tsai, and W.-T. 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IEEE VLSI Test Symp., pp.221-226, May 2009. 10.1109\/vts.2009.45","DOI":"10.1109\/VTS.2009.45"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[19] Z. Xie, H. Li, X. Xu, J. Hu, and Y. Chen, \u201cFast IR drop estimation with machine learning,\u201d Proc. IEEE\/ACM Int. Conf. Comput.-Aided Design, Paper 1D.2, Nov. 2020. 10.1145\/3400302.3415763","DOI":"10.1145\/3400302.3415763"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[20] S. Holst, M.E. Imhof, and H.-J. Wunderlich, \u201cHigh-throughput logic timing simulation on GPGPUs,\u201d ACM Trans. Design Autom. Electron. Syst., vol.20, no.3, pp.1-22, June 2015,. 10.1145\/2714564","DOI":"10.1145\/2714564"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[21] S. Seo, Y. Lee, H. Lim, J. Lee, H. Yoo, Y. Kim, and S. Kang, \u201cScan chain reordering-aware X-filling and stitching for scan shift power reduction,\u201d Proc. IEEE Asian Test Symp., pp.1-6, Nov. 2015. 10.1109\/ats.2015.8","DOI":"10.1109\/ATS.2015.8"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[22] M.-H. Tsai, W.-S. Ding, H.-Y. Hsieh, and J.C.-M. Li, \u201cTransient IR-drop analysis for at-speed testing using representative random walk,\u201d IEEE Trans. Very Large Scale Integr. Syst., vol.22, no.9, pp.1980-1989, Sept. 2014. 10.1109\/tvlsi.2013.2280616","DOI":"10.1109\/TVLSI.2013.2280616"},{"key":"22","unstructured":"[23] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, \u201cA gated clock scheme for low power scan testing of logic ICs or embedded cores,\u201d Proc. IEEE Asian Test Symp., pp.253-258, Nov. 2001. 10.1109\/ats.2001.990291"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[24] Y. Yamato, X. Wen, M.A. Kochte, K. Miyase, S. Kajihara, and L.-T. Wang, \u201cLCTI-SS: Low-clock-tree-impact scan segmentation for avoiding shift timing failures in scan testing,\u201d IEEE Design Test, vol.30, no.4, pp.60-70, Aug. 2013. 10.1109\/mdt.2012.2221152","DOI":"10.1109\/MDT.2012.2221152"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[25] Y. Zhang, X. Wen, S. Holst, K. Miyase, S. Kajihara, H.-J. Wunderlich, and J. Qian, \u201cClock-skew-aware scan chain grouping for mitigating shift timing failures in low-power scan testing,\u201d Proc. IEEE Asian Test Symp., pp.149-154, Oct. 2018. 10.1109\/ats.2018.00037","DOI":"10.1109\/ATS.2018.00037"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[26] S. Almukhaizim and O. Sinanoglu, \u201cPeak power reduction through dynamic partitioning of scan chains,\u201d Proc. IEEE Int. Test Conf., Paper 9.2, Oct. 2008. 10.1109\/test.2008.4700573","DOI":"10.1109\/TEST.2008.4700573"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[27] S. Holst, S. Shi, and X. Wen, \u201cTargeted partial-shift for mitigating shift switching activity hot-spots during scan test,\u201d Proc. IEEE Pacific Rim Int. Symp. Dependable Comput., pp.124-129, Dec. 2019. 10.1109\/prdc47002.2019.00042","DOI":"10.1109\/PRDC47002.2019.00042"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[28] R. Goldman, K. Bartleson, T. Wood, K. Kranen, C. Cao, V. Melikyan, and G. Markosyan, \u201cSynopsys' open educational design kit: capabilities, deployment and future,\u201d Proc. IEEE Int. Conf. Microelectronic Syst. Educ., pp.20-24, July 2009. 10.1109\/mse.2009.5270840","DOI":"10.1109\/MSE.2009.5270840"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E106.D\/10\/E106.D_2023EDP7011\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T19:13:42Z","timestamp":1730229222000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E106.D\/10\/E106.D_2023EDP7011\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,1]]},"references-count":27,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2023]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2023edp7011","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"type":"print","value":"0916-8532"},{"type":"electronic","value":"1745-1361"}],"subject":[],"published":{"date-parts":[[2023,10,1]]},"article-number":"2023EDP7011"}}